📄 shizhong.rpt
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20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\051203005\jilytimer\shizhong.rpt
shizhong
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 24 clk
INPUT 13 clkdsp
Device-Specific Information: f:\051203005\jilytimer\shizhong.rpt
shizhong
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 37 reset
Device-Specific Information: f:\051203005\jilytimer\shizhong.rpt
shizhong
** EQUATIONS **
clk : INPUT;
clkdsp : INPUT;
en : INPUT;
reset : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC1_D16;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC2_D14;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC1_D14;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC5_D11;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = _LC2_D11;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = _LC6_D11;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = _LC8_D9;
-- Node name is 'ss0'
-- Equation name is 'ss0', type is output
ss0 = _LC2_D25;
-- Node name is 'ss1'
-- Equation name is 'ss1', type is output
ss1 = _LC4_D25;
-- Node name is 'ss2'
-- Equation name is 'ss2', type is output
ss2 = _LC8_D25;
-- Node name is 'ss3'
-- Equation name is 'ss3', type is output
ss3 = _LC6_D23;
-- Node name is 'ss4'
-- Equation name is 'ss4', type is output
ss4 = _LC2_D23;
-- Node name is 'ss5'
-- Equation name is 'ss5', type is output
ss5 = _LC1_D22;
-- Node name is '|CNTM24V:1|LPM_ADD_SUB:148|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_D8', type is buried
_LC7_D8 = LCELL( _EQ001);
_EQ001 = _LC1_D8 & _LC5_D8;
-- Node name is '|CNTM24V:1|LPM_ADD_SUB:173|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_D12', type is buried
_LC7_D12 = LCELL( _EQ002);
_EQ002 = _LC1_D15 & _LC2_D12;
-- Node name is '|CNTM24V:1|LPM_ADD_SUB:173|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_D12', type is buried
_LC8_D12 = LCELL( _EQ003);
_EQ003 = _LC1_D15 & _LC2_D12 & _LC5_D12;
-- Node name is '|CNTM24V:1|:16' = '|CNTM24V:1|temp_qh0'
-- Equation name is '_LC5_D8', type is buried
_LC5_D8 = DFFE( _EQ004, GLOBAL( clk), reset, VCC, VCC);
_EQ004 = _LC5_D8 & !_LC5_D35
# _LC4_D12 & _LC5_D8 & !_LC6_D12
# _LC4_D12 & !_LC5_D8 & _LC6_D12;
-- Node name is '|CNTM24V:1|:15' = '|CNTM24V:1|temp_qh1'
-- Equation name is '_LC1_D8', type is buried
_LC1_D8 = DFFE( _EQ005, GLOBAL( clk), reset, VCC, VCC);
_EQ005 = _LC4_D8 & _LC4_D12
# _LC1_D8 & !_LC5_D35;
-- Node name is '|CNTM24V:1|:14' = '|CNTM24V:1|temp_qh2'
-- Equation name is '_LC2_D8', type is buried
_LC2_D8 = DFFE( _EQ006, GLOBAL( clk), reset, VCC, VCC);
_EQ006 = _LC2_D8 & !_LC5_D35
# _LC4_D12 & _LC6_D8;
-- Node name is '|CNTM24V:1|:13' = '|CNTM24V:1|temp_qh3'
-- Equation name is '_LC3_D8', type is buried
_LC3_D8 = DFFE( _EQ007, GLOBAL( clk), reset, VCC, VCC);
_EQ007 = _LC4_D12 & _LC8_D8
# _LC3_D8 & !_LC5_D35;
-- Node name is '|CNTM24V:1|:20' = '|CNTM24V:1|temp_ql0'
-- Equation name is '_LC1_D15', type is buried
_LC1_D15 = DFFE( _EQ008, GLOBAL( clk), reset, VCC, VCC);
_EQ008 = _LC1_D15 & !_LC5_D35
# !_LC1_D15 & _LC5_D35;
-- Node name is '|CNTM24V:1|:19' = '|CNTM24V:1|temp_ql1'
-- Equation name is '_LC2_D12', type is buried
_LC2_D12 = DFFE( _EQ009, GLOBAL( clk), reset, VCC, VCC);
_EQ009 = _LC1_D12 & _LC1_D15 & !_LC2_D12
# _LC1_D12 & !_LC1_D15 & _LC2_D12
# _LC2_D12 & !_LC5_D35;
-- Node name is '|CNTM24V:1|:18' = '|CNTM24V:1|temp_ql2'
-- Equation name is '_LC5_D12', type is buried
_LC5_D12 = DFFE( _EQ010, GLOBAL( clk), reset, VCC, VCC);
_EQ010 = _LC5_D12 & !_LC5_D35
# _LC1_D12 & _LC5_D12 & !_LC7_D12
# _LC1_D12 & !_LC5_D12 & _LC7_D12;
-- Node name is '|CNTM24V:1|:17' = '|CNTM24V:1|temp_ql3'
-- Equation name is '_LC3_D12', type is buried
_LC3_D12 = DFFE( _EQ011, GLOBAL( clk), reset, VCC, VCC);
_EQ011 = _LC3_D12 & !_LC5_D35
# _LC1_D12 & _LC3_D12 & !_LC8_D12
# _LC1_D12 & !_LC3_D12 & _LC8_D12;
-- Node name is '|CNTM24V:1|~106~1'
-- Equation name is '_LC6_D9', type is buried
-- synthesized logic cell
_LC6_D9 = LCELL( _EQ012);
_EQ012 = _LC3_D12
# !_LC1_D8
# _LC5_D12;
-- Node name is '|CNTM24V:1|~106~2'
-- Equation name is '_LC1_D9', type is buried
-- synthesized logic cell
_LC1_D9 = LCELL( _EQ013);
_EQ013 = _LC2_D8
# _LC6_D9
# _LC3_D8
# _LC5_D8;
-- Node name is '|CNTM24V:1|:111'
-- Equation name is '_LC6_D12', type is buried
!_LC6_D12 = _LC6_D12~NOT;
_LC6_D12~NOT = LCELL( _EQ014);
_EQ014 = !_LC3_D12
# !_LC1_D15
# _LC5_D12
# _LC2_D12;
-- Node name is '|CNTM24V:1|:191'
-- Equation name is '_LC8_D8', type is buried
_LC8_D8 = LCELL( _EQ015);
_EQ015 = _LC3_D8 & !_LC6_D12
# _LC3_D8 & !_LC7_D8
# !_LC2_D8 & _LC3_D8
# _LC2_D8 & !_LC3_D8 & _LC6_D12 & _LC7_D8;
-- Node name is '|CNTM24V:1|:203'
-- Equation name is '_LC6_D8', type is buried
_LC6_D8 = LCELL( _EQ016);
_EQ016 = _LC2_D8 & !_LC5_D8
# !_LC1_D8 & _LC2_D8
# _LC1_D8 & !_LC2_D8 & _LC5_D8 & _LC6_D12
# _LC2_D8 & !_LC6_D12;
-- Node name is '|CNTM24V:1|:212'
-- Equation name is '_LC4_D8', type is buried
_LC4_D8 = LCELL( _EQ017);
_EQ017 = !_LC1_D8 & _LC5_D8 & _LC6_D12
# _LC1_D8 & !_LC5_D8
# _LC1_D8 & !_LC6_D12;
-- Node name is '|CNTM24V:1|~281~1'
-- Equation name is '_LC4_D12', type is buried
-- synthesized logic cell
_LC4_D12 = LCELL( _EQ018);
_EQ018 = !_LC1_D15 & _LC5_D35
# !_LC2_D12 & _LC5_D35
# _LC1_D9 & _LC5_D35;
-- Node name is '|CNTM24V:1|~305~1'
-- Equation name is '_LC1_D12', type is buried
-- synthesized logic cell
_LC1_D12 = LCELL( _EQ019);
_EQ019 = _LC4_D12 & !_LC6_D12;
-- Node name is '|CNTM60V:2|LPM_ADD_SUB:148|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_D34', type is buried
_LC5_D34 = LCELL( _EQ020);
_EQ020 = _LC1_D30 & _LC7_D30;
-- Node name is '|CNTM60V:2|LPM_ADD_SUB:173|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_D30', type is buried
_LC4_D30 = LCELL( _EQ021);
_EQ021 = _LC3_D19 & _LC6_D30;
-- Node name is '|CNTM60V:2|LPM_ADD_SUB:173|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_D19', type is buried
_LC4_D19 = LCELL( _EQ022);
_EQ022 = _LC5_D19 & !_LC6_D30
# !_LC3_D19 & _LC5_D19
# !_LC2_D30 & _LC5_D19
# _LC2_D30 & _LC3_D19 & !_LC5_D19 & _LC6_D30;
-- Node name is '|CNTM60V:2|:16' = '|CNTM60V:2|temp_qh0'
-- Equation name is '_LC7_D30', type is buried
_LC7_D30 = DFFE( _EQ023, GLOBAL( clk), reset, VCC, VCC);
_EQ023 = !_LC2_D19 & _LC7_D30
# en & _LC2_D19 & !_LC7_D30
# !en & _LC7_D30;
-- Node name is '|CNTM60V:2|:15' = '|CNTM60V:2|temp_qh1'
-- Equation name is '_LC1_D30', type is buried
_LC1_D30 = DFFE( _EQ024, GLOBAL( clk), reset, VCC, VCC);
_EQ024 = _LC3_D30 & _LC6_D34
# !en & _LC1_D30;
-- Node name is '|CNTM60V:2|:14' = '|CNTM60V:2|temp_qh2'
-- Equation name is '_LC8_D34', type is buried
_LC8_D34 = DFFE( _EQ025, GLOBAL( clk), reset, VCC, VCC);
_EQ025 = _LC4_D34 & _LC6_D34
# !en & _LC8_D34;
-- Node name is '|CNTM60V:2|:13' = '|CNTM60V:2|temp_qh3'
-- Equation name is '_LC1_D34', type is buried
_LC1_D34 = DFFE( _EQ026, GLOBAL( clk), reset, VCC, VCC);
_EQ026 = _LC6_D34 & _LC7_D34
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