cntm24v.vhd

VHDL语言实现时钟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntm24v is
	port(clk,clr,en:in std_logic;
		cont:out std_logic;
		qh,ql:out std_logic_vector(3 downto 0));
end entity cntm24v;
architecture beh of cntm24v is
signal temp_qh,temp_ql:std_logic_vector(3 downto 0);
begin
	qh<=temp_qh;
	ql<=temp_ql;
	cont<='1' when (temp_qh="0010" and temp_ql="0011" and en='1') else '0';
	process(clk,clr)
		begin
			if clr='0' then
				temp_qh<="0000";
				temp_ql<="0000"; 

		elsif(clk'event and clk='1')then
			if en='1'then
				if(temp_qh=2 and temp_ql=3)then
				temp_qh<="0000";
				temp_ql<="0000"; 
				elsif(temp_ql=9)then
				temp_ql<="0000";
				temp_qh<=temp_qh+1;
				else
				temp_ql<=temp_ql+1;
				end if;
				end if;
				
		end if;
	end process;
end architecture beh;