📄 qselect.rpt
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| | +--------------------------- LC22 qout0
| | | +------------------------- LC17 qout1
| | | | +----------------------- LC31 qout2
| | | | | +--------------------- LC32 qout3
| | | | | | +------------------- LC20 qsel0
| | | | | | | +----------------- LC30 qsel1
| | | | | | | | +--------------- LC23 qsel2
| | | | | | | | | +------------- LC24 qsel3
| | | | | | | | | | +----------- LC26 qsel4
| | | | | | | | | | | +--------- LC28 qsel5
| | | | | | | | | | | | +------- LC19 sel2
| | | | | | | | | | | | | +----- LC21 sel1
| | | | | | | | | | | | | | +--- LC25 ~538~1
| | | | | | | | | | | | | | | +- LC18 ~559~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC27 -> - - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node1
LC29 -> - - - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node2
LC19 -> - * * * * * * * * * * * * * * * | - * | <-- sel2
LC21 -> * * * * * * * * * * * * * * * * | - * | <-- sel1
LC25 -> - - - * - - - - - - - - - - - - | - * | <-- ~538~1
LC18 -> - - * - - - - - - - - - - - - - | - * | <-- ~559~1
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
4 -> - - * * * * * * * * * * * * - - | * * | <-- clr
44 -> - - * - - - - - - - - - - - - - | - * | <-- qhh0
40 -> - - - * - - - - - - - - - - - - | - * | <-- qhh1
37 -> - - - - * - - - - - - - - - - - | - * | <-- qhh2
1 -> - - - - - * - - - - - - - - - - | - * | <-- qhh3
32 -> - - - - - - - - - - - - - - - * | - * | <-- qhm0
29 -> - - - - - - - - - - - - - - * - | - * | <-- qhm1
27 -> - - - - * - - - - - - - - - - - | - * | <-- qhm2
2 -> - - - - - * - - - - - - - - - - | - * | <-- qhm3
19 -> - - - - - - - - - - - - - - - * | - * | <-- qhs0
18 -> - - - - - - - - - - - - - - * - | - * | <-- qhs1
17 -> - - - - * - - - - - - - - - - - | - * | <-- qhs2
5 -> - - - - - * - - - - - - - - - - | - * | <-- qhs3
6 -> - - - - - - - - - - - - - - - * | - * | <-- qlh0
7 -> - - - - - - - - - - - - - - * - | - * | <-- qlh1
8 -> - - - - * - - - - - - - - - - - | - * | <-- qlh2
9 -> - - - - - * - - - - - - - - - - | - * | <-- qlh3
11 -> - - - - - - - - - - - - - - - * | - * | <-- qlm0
12 -> - - - - - - - - - - - - - - * - | - * | <-- qlm1
13 -> - - - - * - - - - - - - - - - - | - * | <-- qlm2
14 -> - - - - - * - - - - - - - - - - | - * | <-- qlm3
16 -> - - - - - - - - - - - - - - - * | - * | <-- qls0
39 -> - - - - - - - - - - - - - - * - | - * | <-- qls1
21 -> - - - - * - - - - - - - - - - - | - * | <-- qls2
20 -> - - - - - * - - - - - - - - - - | - * | <-- qls3
LC8 -> * * * * * * * * * * * * * * * * | - * | <-- sel0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2\example\jilytimer\qselect.rpt
qselect
** EQUATIONS **
clk : INPUT;
clr : INPUT;
qhh0 : INPUT;
qhh1 : INPUT;
qhh2 : INPUT;
qhh3 : INPUT;
qhm0 : INPUT;
qhm1 : INPUT;
qhm2 : INPUT;
qhm3 : INPUT;
qhs0 : INPUT;
qhs1 : INPUT;
qhs2 : INPUT;
qhs3 : INPUT;
qlh0 : INPUT;
qlh1 : INPUT;
qlh2 : INPUT;
qlh3 : INPUT;
qlm0 : INPUT;
qlm1 : INPUT;
qlm2 : INPUT;
qlm3 : INPUT;
qls0 : INPUT;
qls1 : INPUT;
qls2 : INPUT;
qls3 : INPUT;
-- Node name is 'qout0' = ':33'
-- Equation name is 'qout0', type is output
qout0 = DFFE( _EQ001 $ VCC, GLOBAL( clk), clr, VCC, VCC);
_EQ001 = !_LC018 & _X001;
_X001 = EXP( qhh0 & !sel0 & !sel1 & !sel2);
-- Node name is 'qout1' = ':31'
-- Equation name is 'qout1', type is output
qout1 = DFFE( _EQ002 $ VCC, GLOBAL( clk), clr, VCC, VCC);
_EQ002 = !_LC025 & _X002;
_X002 = EXP( qhh1 & !sel0 & !sel1 & !sel2);
-- Node name is 'qout2' = ':29'
-- Equation name is 'qout2', type is output
qout2 = DFFE( _EQ003 $ VCC, GLOBAL( clk), clr, VCC, VCC);
_EQ003 = _X003 & _X004 & _X005 & _X006 & _X007 & _X008;
_X003 = EXP( qls2 & sel0 & !sel1 & sel2);
_X004 = EXP( qlm2 & sel0 & sel1 & !sel2);
_X005 = EXP( qlh2 & sel0 & !sel1 & !sel2);
_X006 = EXP( qhm2 & !sel0 & sel1 & !sel2);
_X007 = EXP( qhs2 & !sel0 & !sel1 & sel2);
_X008 = EXP( qhh2 & !sel0 & !sel1 & !sel2);
-- Node name is 'qout3' = ':27'
-- Equation name is 'qout3', type is output
qout3 = DFFE( _EQ004 $ VCC, GLOBAL( clk), clr, VCC, VCC);
_EQ004 = _X009 & _X010 & _X011 & _X012 & _X013 & _X014;
_X009 = EXP( qls3 & sel0 & !sel1 & sel2);
_X010 = EXP( qlm3 & sel0 & sel1 & !sel2);
_X011 = EXP( qlh3 & sel0 & !sel1 & !sel2);
_X012 = EXP( qhm3 & !sel0 & sel1 & !sel2);
_X013 = EXP( qhs3 & !sel0 & !sel1 & sel2);
_X014 = EXP( qhh3 & !sel0 & !sel1 & !sel2);
-- Node name is 'qsel0' = ':45'
-- Equation name is 'qsel0', type is output
qsel0 = DFFE( _EQ005 $ !sel2, GLOBAL( clk), VCC, clr, VCC);
_EQ005 = !sel0 & !sel1 & sel2;
-- Node name is 'qsel1' = ':43'
-- Equation name is 'qsel1', type is output
qsel1 = DFFE( _EQ006 $ !sel2, GLOBAL( clk), VCC, clr, VCC);
_EQ006 = sel0 & !sel1 & sel2;
-- Node name is 'qsel2' = ':41'
-- Equation name is 'qsel2', type is output
qsel2 = DFFE( _EQ007 $ !sel1, GLOBAL( clk), VCC, clr, VCC);
_EQ007 = !sel0 & sel1 & !sel2;
-- Node name is 'qsel3' = ':39'
-- Equation name is 'qsel3', type is output
qsel3 = DFFE( _EQ008 $ !sel1, GLOBAL( clk), VCC, clr, VCC);
_EQ008 = sel0 & sel1 & !sel2;
-- Node name is 'qsel4' = ':37'
-- Equation name is 'qsel4', type is output
qsel4 = DFFE( _EQ009 $ VCC, GLOBAL( clk), VCC, clr, VCC);
_EQ009 = sel0 & !sel1 & !sel2
# sel1 & sel2;
-- Node name is 'qsel5' = ':35'
-- Equation name is 'qsel5', type is output
qsel5 = DFFE( _EQ010 $ VCC, GLOBAL( clk), VCC, clr, VCC);
_EQ010 = !sel0 & !sel1 & !sel2
# sel1 & sel2;
-- Node name is ':49' = 'sel0'
-- Equation name is 'sel0', location is LC008, type is buried.
sel0 = TFFE( VCC, GLOBAL( clk), clr, VCC, VCC);
-- Node name is ':48' = 'sel1'
-- Equation name is 'sel1', location is LC021, type is buried.
sel1 = DFFE( _EQ011 $ _LC027, GLOBAL( clk), clr, VCC, VCC);
_EQ011 = _LC027 & sel0 & !sel1 & sel2;
-- Node name is ':47' = 'sel2'
-- Equation name is 'sel2', location is LC019, type is buried.
sel2 = DFFE( _EQ012 $ _LC029, GLOBAL( clk), clr, VCC, VCC);
_EQ012 = _LC029 & sel0 & !sel1 & sel2;
-- Node name is '|LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( sel1 $ sel0);
-- Node name is '|LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( sel2 $ _EQ013);
_EQ013 = sel0 & sel1;
-- Node name is '~538~1'
-- Equation name is '~538~1', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ014 $ GND);
_EQ014 = qlm1 & sel0 & sel1 & !sel2
# qls1 & sel0 & !sel1 & sel2
# qlh1 & sel0 & !sel1 & !sel2
# qhm1 & !sel0 & sel1 & !sel2
# qhs1 & !sel0 & !sel1 & sel2;
-- Node name is '~559~1'
-- Equation name is '~559~1', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ015 $ GND);
_EQ015 = qlm0 & sel0 & sel1 & !sel2
# qls0 & sel0 & !sel1 & sel2
# qlh0 & sel0 & !sel1 & !sel2
# qhm0 & !sel0 & sel1 & !sel2
# qhs0 & !sel0 & !sel1 & sel2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\maxplus2\example\jilytimer\qselect.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,568K
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