📄 qselect.rpt
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Project Information d:\maxplus2\example\jilytimer\qselect.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 06/24/2008 21:44:15
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
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***** Project compilation was successful
QSELECT
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
qselect EPM7032LC44-6 26 10 0 17 14 53 %
User Pins: 26 10 0
Project Information d:\maxplus2\example\jilytimer\qselect.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information d:\maxplus2\example\jilytimer\qselect.rpt
** FILE HIERARCHY **
|lpm_add_sub:95|
|lpm_add_sub:95|addcore:adder|
|lpm_add_sub:95|addcore:adder|addcore:adder0|
|lpm_add_sub:95|altshift:result_ext_latency_ffs|
|lpm_add_sub:95|altshift:carry_ext_latency_ffs|
|lpm_add_sub:95|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\maxplus2\example\jilytimer\qselect.rpt
qselect
***** Logic for device 'qselect' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Device-Specific Information: d:\maxplus2\example\jilytimer\qselect.rpt
qselect
** ERROR SUMMARY **
Info: Chip 'qselect' in device 'EPM7032LC44-6' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
q
q q q q q o q
l h c V h h h c G u h
h s l C m h h l N t h
0 3 r C 3 3 0 k D 1 1
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
qlh1 | 7 39 | qls1
qlh2 | 8 38 | qsel0
qlh3 | 9 37 | qhh2
GND | 10 36 | qout0
qlm0 | 11 35 | VCC
qlm1 | 12 EPM7032LC44-6 34 | qsel2
qlm2 | 13 33 | qsel3
qlm3 | 14 32 | qhm0
VCC | 15 31 | qsel4
qls0 | 16 30 | GND
qhs2 | 17 29 | qhm1
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
q q q q G V q q q q q
h h l l N C o o s h s
s s s s D C u u e m e
1 0 3 2 t t l 2 l
3 2 1 5
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\maxplus2\example\jilytimer\qselect.rpt
qselect
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 1/16( 6%) 16/16(100%) 0/16( 0%) 1/36( 2%)
B: LC17 - LC32 16/16(100%) 16/16(100%) 16/16(100%) 32/36( 88%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 17/32 ( 53%)
Total shareable expanders used: 14/32 ( 43%)
Total Turbo logic cells used: 17/32 ( 53%)
Total shareable expanders not available (n/a): 2/32 ( 6%)
Average fan-in: 6.00
Total fan-in: 102
Total input pins required: 26
Total output pins required: 10
Total bidirectional pins required: 0
Total logic cells required: 17
Total flipflops required: 13
Total product terms required: 62
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 14
Synthesized logic cells: 2/ 32 ( 6%)
Device-Specific Information: d:\maxplus2\example\jilytimer\qselect.rpt
qselect
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 clk
4 (1) (A) INPUT 0 0 0 0 0 10 3 clr
44 - - INPUT 0 0 0 0 0 1 0 qhh0
40 (18) (B) INPUT 0 0 0 0 0 1 0 qhh1
37 (21) (B) INPUT 0 0 0 0 0 1 0 qhh2
1 - - INPUT 0 0 0 0 0 1 0 qhh3
32 (25) (B) INPUT 0 0 0 0 0 0 1 qhm0
29 (27) (B) INPUT 0 0 0 0 0 0 1 qhm1
27 (29) (B) INPUT 0 0 0 0 0 1 0 qhm2
2 - - INPUT 0 0 0 0 0 1 0 qhm3
19 (14) (A) INPUT 0 0 0 0 0 0 1 qhs0
18 (13) (A) INPUT 0 0 0 0 0 0 1 qhs1
17 (12) (A) INPUT 0 0 0 0 0 1 0 qhs2
5 (2) (A) INPUT 0 0 0 0 0 1 0 qhs3
6 (3) (A) INPUT 0 0 0 0 0 0 1 qlh0
7 (4) (A) INPUT 0 0 0 0 0 0 1 qlh1
8 (5) (A) INPUT 0 0 0 0 0 1 0 qlh2
9 (6) (A) INPUT 0 0 0 0 0 1 0 qlh3
11 (7) (A) INPUT 0 0 0 0 0 0 1 qlm0
12 (8) (A) INPUT 0 0 0 0 0 0 1 qlm1
13 (9) (A) INPUT 0 0 0 0 0 1 0 qlm2
14 (10) (A) INPUT 0 0 0 0 0 1 0 qlm3
16 (11) (A) INPUT 0 0 0 0 0 0 1 qls0
39 (19) (B) INPUT 0 0 0 0 0 0 1 qls1
21 (16) (A) INPUT 0 0 0 0 0 1 0 qls2
20 (15) (A) INPUT 0 0 0 0 0 1 0 qls3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\maxplus2\example\jilytimer\qselect.rpt
qselect
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
36 22 B FF + t 1 0 0 2 4 0 0 qout0
41 17 B FF + t 1 0 0 2 4 0 0 qout1
25 31 B FF + t 6 0 0 7 3 0 0 qout2
24 32 B FF + t 6 0 0 7 3 0 0 qout3
38 20 B FF + t 0 0 0 1 3 0 0 qsel0
26 30 B FF + t 0 0 0 1 3 0 0 qsel1
34 23 B FF + t 0 0 0 1 3 0 0 qsel2
33 24 B FF + t 0 0 0 1 3 0 0 qsel3
31 26 B FF + t 0 0 0 1 3 0 0 qsel4
28 28 B FF + t 0 0 0 1 3 0 0 qsel5
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2\example\jilytimer\qselect.rpt
qselect
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(29) 27 B SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node1
(27) 29 B SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node2
(39) 19 B DFFE + t 0 0 0 1 4 10 5 sel2 (:47)
(37) 21 B DFFE + t 0 0 0 1 4 10 6 sel1 (:48)
(12) 8 A TFFE + t 0 0 0 1 0 10 6 sel0 (:49)
(32) 25 B SOFT s t 1 0 1 5 3 1 0 ~538~1
(40) 18 B SOFT s t 1 0 1 5 3 1 0 ~559~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2\example\jilytimer\qselect.rpt
qselect
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC8 sel0
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B | Logic cells that feed LAB 'A':
Pin
43 -> - | - - | <-- clk
4 -> * | * * | <-- clr
44 -> - | - * | <-- qhh0
1 -> - | - * | <-- qhh3
2 -> - | - * | <-- qhm3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2\example\jilytimer\qselect.rpt
qselect
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC27 |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node1
| +----------------------------- LC29 |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node2
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