📄 counter32b.rpt
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| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC4 -> - * - - - - - - | * - * * | <-- DOUT13
LC5 -> - - * - - - - - | * - * * | <-- DOUT14
LC8 -> - - - * - - - - | * - * * | <-- DOUT15
LC1 -> - - - - * - - - | * - - * | <-- DOUT21
LC16 -> - - - - - * - - | * - - * | <-- DOUT29
LC14 -> - - - - - - * - | * - - * | <-- DOUT30
LC11 -> - - - - - - - * | * - - * | <-- DOUT31
Pin
44 -> * * * * * * * * | * * * * | <-- CLR
1 -> * * * * * * * * | * * * * | <-- ENABL
43 -> - - - - - - - - | - - - - | <-- FIN
LC43 -> - * - - - - - - | * - - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node5
LC39 -> - - * - - - - - | * - - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node6
LC34 -> - - - * - - - - | * - - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node7
LC55 -> - - - - * - - - | * - - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node5
LC58 -> - - - - - * - - | * - - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node5
LC61 -> - - - - - - * - | * - - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node6
LC63 -> - - - - - - - * | * - - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\work5 freqtest\counter32b.rpt
counter32b
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------- LC24 DOUT1
| +------------- LC30 DOUT2
| | +----------- LC19 DOUT3
| | | +--------- LC25 DOUT5
| | | | +------- LC32 DOUT6
| | | | | +----- LC17 DOUT7
| | | | | | +--- LC20 DOUT22
| | | | | | | +- LC21 DOUT23
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'B'
LC | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC24 -> * * * - - - - - | - * * - | <-- DOUT1
LC30 -> - * * - - - - - | - * * - | <-- DOUT2
LC25 -> - - - * - - - - | - * * - | <-- DOUT5
LC32 -> - - - - * - - - | - * * - | <-- DOUT6
LC17 -> - - - - - * - - | - * * - | <-- DOUT7
LC20 -> - - - - - - * - | - * - * | <-- DOUT22
LC21 -> - - - - - - - * | - * - * | <-- DOUT23
Pin
44 -> * * * * * * * * | * * * * | <-- CLR
1 -> * * * * * * * * | * * * * | <-- ENABL
43 -> - - - - - - - - | - - - - | <-- FIN
LC3 -> * * * - - - - - | - * * - | <-- DOUT0
LC45 -> - - - * - - - - | - * - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node5
LC44 -> - - - - * - - - | - * - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node6
LC38 -> - - - - - * - - | - * - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node7
LC60 -> - - - - - - * - | - * - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node6
LC59 -> - - - - - - - * | - * - - | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\work5 freqtest\counter32b.rpt
counter32b
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC37 DOUT4
| +----------------------------- LC36 DOUT8
| | +--------------------------- LC33 DOUT9
| | | +------------------------- LC48 DOUT10
| | | | +----------------------- LC46 DOUT11
| | | | | +--------------------- LC40 DOUT12
| | | | | | +------------------- LC35 DOUT16
| | | | | | | +----------------- LC41 DOUT17
| | | | | | | | +--------------- LC42 |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|cout_node
| | | | | | | | | +------------- LC45 |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | | +----------- LC44 |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node6
| | | | | | | | | | | +--------- LC38 |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node7
| | | | | | | | | | | | +------- LC47 |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|cout_node
| | | | | | | | | | | | | +----- LC43 |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node5
| | | | | | | | | | | | | | +--- LC39 |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node6
| | | | | | | | | | | | | | | +- LC34 |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node7
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC37 -> * * * * * * * - * * * * * * * * | - - * - | <-- DOUT4
LC36 -> - * * * * * * * - - - - * * * * | - - * * | <-- DOUT8
LC33 -> - - * * * * * * - - - - * * * * | - - * * | <-- DOUT9
LC48 -> - - - * * * * * - - - - * * * * | - - * * | <-- DOUT10
LC46 -> - - - - * * * * - - - - * * * * | - - * * | <-- DOUT11
LC40 -> - - - - - * * * - - - - * * * * | - - * * | <-- DOUT12
LC35 -> - - - - - - * * - - - - - - - - | - - * * | <-- DOUT16
LC42 -> - - - - - - - * - - - - - - - - | - - * * | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|cout_node
Pin
44 -> * * * * * * * * - - - - - - - - | * * * * | <-- CLR
1 -> * * * * * * * * - - - - - - - - | * * * * | <-- ENABL
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- FIN
LC3 -> * * * * * * * - * * * * * * * * | - * * - | <-- DOUT0
LC24 -> * * * * * * * - * * * * * * * * | - * * - | <-- DOUT1
LC30 -> * * * * * * * - * * * * * * * * | - * * - | <-- DOUT2
LC19 -> * * * * * * * - * * * * * * * * | - - * - | <-- DOUT3
LC25 -> - * * * * * * - * * * * * * * * | - * * - | <-- DOUT5
LC32 -> - * * * * * * - * - * * * * * * | - * * - | <-- DOUT6
LC17 -> - * * * * * * - * - - * * * * * | - * * - | <-- DOUT7
LC4 -> - - - - - - * * - - - - * * * * | * - * * | <-- DOUT13
LC5 -> - - - - - - * * - - - - * - * * | * - * * | <-- DOUT14
LC8 -> - - - - - - * * - - - - * - - * | * - * * | <-- DOUT15
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\work5 freqtest\counter32b.rpt
counter32b
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------------- LC57 DOUT18
| +--------------------------- LC51 DOUT19
| | +------------------------- LC64 DOUT20
| | | +----------------------- LC53 DOUT24
| | | | +--------------------- LC56 DOUT25
| | | | | +------------------- LC52 DOUT26
| | | | | | +----------------- LC62 DOUT27
| | | | | | | +--------------- LC49 DOUT28
| | | | | | | | +------------- LC50 |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|cout_node
| | | | | | | | | +----------- LC55 |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node5
| | | | | | | | | | +--------- LC60 |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node6
| | | | | | | | | | | +------- LC59 |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node7
| | | | | | | | | | | | +----- LC58 |LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node5
| | | | | | | | | | | | | +--- LC61 |LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node6
| | | | | | | | | | | | | | +- LC63 |LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node7
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC57 -> * * * * * * * - * * * * * * * | - - - * | <-- DOUT18
LC51 -> - * * * * * * - * * * * * * * | - - - * | <-- DOUT19
LC64 -> - - * * * * * - * * * * * * * | - - - * | <-- DOUT20
LC53 -> - - - * * * * * - - - - * * * | - - - * | <-- DOUT24
LC56 -> - - - - * * * * - - - - * * * | - - - * | <-- DOUT25
LC52 -> - - - - - * * * - - - - * * * | - - - * | <-- DOUT26
LC62 -> - - - - - - * * - - - - * * * | - - - * | <-- DOUT27
LC49 -> - - - - - - - * - - - - * * * | - - - * | <-- DOUT28
LC50 -> - - - - - - - * - - - - - - - | - - - * | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|cout_node
Pin
44 -> * * * * * * * * - - - - - - - | * * * * | <-- CLR
1 -> * * * * * * * * - - - - - - - | * * * * | <-- ENABL
43 -> - - - - - - - - - - - - - - - | - - - - | <-- FIN
LC36 -> * * * - - - - - * * * * - - - | - - * * | <-- DOUT8
LC33 -> * * * - - - - - * * * * - - - | - - * * | <-- DOUT9
LC48 -> * * * - - - - - * * * * - - - | - - * * | <-- DOUT10
LC46 -> * * * - - - - - * * * * - - - | - - * * | <-- DOUT11
LC40 -> * * * - - - - - * * * * - - - | - - * * | <-- DOUT12
LC4 -> * * * - - - - - * * * * - - - | * - * * | <-- DOUT13
LC5 -> * * * - - - - - * * * * - - - | * - * * | <-- DOUT14
LC8 -> * * * - - - - - * * * * - - - | * - * * | <-- DOUT15
LC35 -> * * * * * * * - * * * * * * * | - - * * | <-- DOUT16
LC41 -> * * * * * * * - * * * * * * * | - - - * | <-- DOUT17
LC1 -> - - - * * * * - * * * * * * * | * - - * | <-- DOUT21
LC20 -> - - - * * * * - * - * * * * * | - * - * | <-- DOUT22
LC21 -> - - - * * * * - * - - * * * * | - * - * | <-- DOUT23
LC16 -> - - - - - - - - - - - - * * * | * - - * | <-- DOUT29
LC14 -> - - - - - - - - - - - - - * * | * - - * | <-- DOUT30
LC11 -> - - - - - - - - - - - - - - * | * - - * | <-- DOUT31
LC42 -> * * * - - - - - * * * * - - - | - - * * | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|cout_node
LC47 -> - - - * * * * - - - - - * * * | - - - * | <-- |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|cout_node
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\work5 freqtest\counter32b.rpt
counter32b
** EQUATIONS **
CLR : INPUT;
ENABL : INPUT;
FIN : INPUT;
-- Node name is 'DOUT0' = 'CQI0'
-- Equation name is 'DOUT0', location is LC003, type is output.
DOUT0 = TFFE( ENABL, GLOBAL( FIN), !CLR, VCC, VCC);
-- Node name is 'DOUT1' = 'CQI1'
-- Equation name is 'DOUT1', location is LC024, type is output.
DOUT1 = TFFE( _EQ001, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ001 = DOUT0 & ENABL;
-- Node name is 'DOUT2' = 'CQI2'
-- Equation name is 'DOUT2', location is LC030, type is output.
DOUT2 = TFFE( _EQ002, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ002 = DOUT0 & DOUT1 & ENABL;
-- Node name is 'DOUT3' = 'CQI3'
-- Equation name is 'DOUT3', location is LC019, type is output.
DOUT3 = TFFE( _EQ003, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ003 = DOUT0 & DOUT1 & DOUT2 & ENABL;
-- Node name is 'DOUT4' = 'CQI4'
-- Equation name is 'DOUT4', location is LC037, type is output.
DOUT4 = TFFE( _EQ004, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ004 = DOUT0 & DOUT1 & DOUT2 & DOUT3 & ENABL;
-- Node name is 'DOUT5' = 'CQI5'
-- Equation name is 'DOUT5', location is LC025, type is output.
DOUT5 = DFFE( _EQ005 $ GND, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ005 = ENABL & _LC045
# DOUT5 & !ENABL;
-- Node name is 'DOUT6' = 'CQI6'
-- Equation name is 'DOUT6', location is LC032, type is output.
DOUT6 = DFFE( _EQ006 $ GND, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ006 = ENABL & _LC044
# DOUT6 & !ENABL;
-- Node name is 'DOUT7' = 'CQI7'
-- Equation name is 'DOUT7', location is LC017, type is output.
DOUT7 = DFFE( _EQ007 $ GND, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ007 = ENABL & _LC038
# DOUT7 & !ENABL;
-- Node name is 'DOUT8' = 'CQI8'
-- Equation name is 'DOUT8', location is LC036, type is output.
DOUT8 = TFFE( _EQ008, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ008 = DOUT0 & DOUT1 & DOUT2 & DOUT3 & DOUT4 & DOUT5 & DOUT6 &
DOUT7 & ENABL;
-- Node name is 'DOUT9' = 'CQI9'
-- Equation name is 'DOUT9', location is LC033, type is output.
DOUT9 = TFFE( _EQ009, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ009 = DOUT0 & DOUT1 & DOUT2 & DOUT3 & DOUT4 & DOUT5 & DOUT6 &
DOUT7 & DOUT8 & ENABL;
-- Node name is 'DOUT10' = 'CQI10'
-- Equation name is 'DOUT10', location is LC048, type is output.
DOUT10 = TFFE( _EQ010, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ010 = DOUT0 & DOUT1 & DOUT2 & DOUT3 & DOUT4 & DOUT5 & DOUT6 &
DOUT7 & DOUT8 & DOUT9 & ENABL;
-- Node name is 'DOUT11' = 'CQI11'
-- Equation name is 'DOUT11', location is LC046, type is output.
DOUT11 = TFFE( _EQ011, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ011 = DOUT0 & DOUT1 & DOUT2 & DOUT3 & DOUT4 & DOUT5 & DOUT6 &
DOUT7 & DOUT8 & DOUT9 & DOUT10 & ENABL;
-- Node name is 'DOUT12' = 'CQI12'
-- Equation name is 'DOUT12', location is LC040, type is output.
DOUT12 = TFFE( _EQ012, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ012 = DOUT0 & DOUT1 & DOUT2 & DOUT3 & DOUT4 & DOUT5 & DOUT6 &
DOUT7 & DOUT8 & DOUT9 & DOUT10 & DOUT11 & ENABL;
-- Node name is 'DOUT13' = 'CQI13'
-- Equation name is 'DOUT13', location is LC004, type is output.
DOUT13 = DFFE( _EQ013 $ GND, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ013 = ENABL & _LC043
# DOUT13 & !ENABL;
-- Node name is 'DOUT14' = 'CQI14'
-- Equation name is 'DOUT14', location is LC005, type is output.
DOUT14 = DFFE( _EQ014 $ GND, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ014 = ENABL & _LC039
# DOUT14 & !ENABL;
-- Node name is 'DOUT15' = 'CQI15'
-- Equation name is 'DOUT15', location is LC008, type is output.
DOUT15 = DFFE( _EQ015 $ GND, GLOBAL( FIN), !CLR, VCC, VCC);
_EQ015 = ENABL & _LC034
# DOUT15 & !ENABL;
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