📄 counter32b.rpt
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Project Information d:\vhdl\work5 freqtest\counter32b.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/21/2008 09:43:45
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
COUNTER32B
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
counter32b
EPM7064LC44-7 3 32 0 47 0 73 %
User Pins: 3 32 0
Project Information d:\vhdl\work5 freqtest\counter32b.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'FIN' chosen for auto global Clock
Project Information d:\vhdl\work5 freqtest\counter32b.rpt
** FILE HIERARCHY **
|lpm_add_sub:298|
|lpm_add_sub:298|addcore:adder|
|lpm_add_sub:298|addcore:adder|addcore:adder3|
|lpm_add_sub:298|addcore:adder|addcore:adder2|
|lpm_add_sub:298|addcore:adder|addcore:adder1|
|lpm_add_sub:298|addcore:adder|addcore:adder0|
|lpm_add_sub:298|altshift:result_ext_latency_ffs|
|lpm_add_sub:298|altshift:carry_ext_latency_ffs|
|lpm_add_sub:298|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\vhdl\work5 freqtest\counter32b.rpt
counter32b
***** Logic for device 'counter32b' compiled without errors.
Device: EPM7064LC44-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
Device-Specific Information: d:\vhdl\work5 freqtest\counter32b.rpt
counter32b
** ERROR SUMMARY **
Info: Chip 'counter32b' in device 'EPM7064LC44-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
D D D D D
O O O E O O
U U U N U U
T T T V G A C F G T T
3 3 2 C N B L I N 2 2
1 0 9 C D L R N D 0 7
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
DOUT15 | 7 39 | DOUT18
DOUT14 | 8 38 | DOUT25
DOUT13 | 9 37 | DOUT24
GND | 10 36 | DOUT26
DOUT0 | 11 35 | VCC
DOUT21 | 12 EPM7064LC44-7 34 | DOUT19
DOUT6 | 13 33 | DOUT28
DOUT2 | 14 32 | DOUT10
VCC | 15 31 | DOUT11
DOUT5 | 16 30 | GND
DOUT1 | 17 29 | DOUT17
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
D D D D G V D D D D D
O O O O N C O O O O O
U U U U D C U U U U U
T T T T T T T T T
2 2 3 7 9 1 8 4 1
3 2 6 2
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\vhdl\work5 freqtest\counter32b.rpt
counter32b
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 8/16( 50%) 8/ 8(100%) 0/16( 0%) 16/36( 44%)
B: LC17 - LC32 8/16( 50%) 8/ 8(100%) 0/16( 0%) 15/36( 41%)
C: LC33 - LC48 16/16(100%) 8/ 8(100%) 0/16( 0%) 20/36( 55%)
D: LC49 - LC64 15/16( 93%) 8/ 8(100%) 0/16( 0%) 29/36( 80%)
Total dedicated input pins used: 3/4 ( 75%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 47/64 ( 73%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 47/64 ( 73%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 10.89
Total fan-in: 512
Total input pins required: 3
Total output pins required: 32
Total bidirectional pins required: 0
Total logic cells required: 47
Total flipflops required: 32
Total product terms required: 103
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: d:\vhdl\work5 freqtest\counter32b.rpt
counter32b
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
44 - - INPUT 0 0 0 0 0 32 0 CLR
1 - - INPUT 0 0 0 0 0 32 0 ENABL
43 - - INPUT G 0 0 0 0 0 0 0 FIN
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\vhdl\work5 freqtest\counter32b.rpt
counter32b
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
11 3 A FF + t 0 0 0 2 0 10 8 DOUT0 (:67)
17 24 B FF + t 0 0 0 2 1 9 8 DOUT1 (:66)
14 30 B FF + t 0 0 0 2 2 8 8 DOUT2 (:65)
20 19 B FF + t 0 0 0 2 3 7 8 DOUT3 (:64)
27 37 C FF + t 0 0 0 2 4 6 8 DOUT4 (:63)
16 25 B FF + t 0 0 0 2 2 7 8 DOUT5 (:62)
13 32 B FF + t 0 0 0 2 2 7 7 DOUT6 (:61)
21 17 B FF + t 0 0 0 2 2 7 6 DOUT7 (:60)
26 36 C FF + t 0 0 0 2 8 9 8 DOUT8 (:59)
24 33 C FF + t 0 0 0 2 9 8 8 DOUT9 (:58)
32 48 C FF + t 0 0 0 2 10 7 8 DOUT10 (:57)
31 46 C FF + t 0 0 0 2 11 6 8 DOUT11 (:56)
28 40 C FF + t 0 0 0 2 12 5 8 DOUT12 (:55)
9 4 A FF + t 0 0 0 2 2 6 8 DOUT13 (:54)
8 5 A FF + t 0 0 0 2 2 6 7 DOUT14 (:53)
7 8 A FF + t 0 0 0 2 2 6 6 DOUT15 (:52)
25 35 C FF + t 0 0 0 2 16 8 7 DOUT16 (:51)
29 41 C FF + t 0 0 0 2 10 7 7 DOUT17 (:50)
39 57 D FF + t 0 0 0 2 11 6 7 DOUT18 (:49)
34 51 D FF + t 0 0 0 2 12 5 7 DOUT19 (:48)
41 64 D FF + t 0 0 0 2 13 4 7 DOUT20 (:47)
12 1 A FF + t 0 0 0 2 2 5 7 DOUT21 (:46)
19 20 B FF + t 0 0 0 2 2 5 6 DOUT22 (:45)
18 21 B FF + t 0 0 0 2 2 5 5 DOUT23 (:44)
37 53 D FF + t 0 0 0 2 9 4 3 DOUT24 (:43)
38 56 D FF + t 0 0 0 2 10 3 3 DOUT25 (:42)
36 52 D FF + t 0 0 0 2 11 2 3 DOUT26 (:41)
40 62 D FF + t 0 0 0 2 12 1 3 DOUT27 (:40)
33 49 D FF + t 0 0 0 2 5 0 3 DOUT28 (:39)
4 16 A FF + t 0 0 0 2 2 1 3 DOUT29 (:38)
5 14 A FF + t 0 0 0 2 2 1 2 DOUT30 (:37)
6 11 A FF + t 0 0 0 2 2 1 1 DOUT31 (:36)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\work5 freqtest\counter32b.rpt
counter32b
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 42 C SOFT t 0 0 0 0 8 4 4 |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|cout_node
- 45 C SOFT t 0 0 0 0 6 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node5
- 44 C SOFT t 0 0 0 0 7 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node6
- 38 C SOFT t 0 0 0 0 8 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node7
- 47 C SOFT t 0 0 0 0 16 4 3 |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|cout_node
- 43 C SOFT t 0 0 0 0 14 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node5
- 39 C SOFT t 0 0 0 0 15 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node6
- 34 C SOFT t 0 0 0 0 16 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node7
- 50 D SOFT t 0 0 0 0 17 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|cout_node
- 55 D SOFT t 0 0 0 0 15 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node5
- 60 D SOFT t 0 0 0 0 16 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node6
- 59 D SOFT t 0 0 0 0 17 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node7
- 58 D SOFT t 0 0 0 0 15 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node5
- 61 D SOFT t 0 0 0 0 16 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node6
- 63 D SOFT t 0 0 0 0 17 1 0 |LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\work5 freqtest\counter32b.rpt
counter32b
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC3 DOUT0
| +------------- LC4 DOUT13
| | +----------- LC5 DOUT14
| | | +--------- LC8 DOUT15
| | | | +------- LC1 DOUT21
| | | | | +----- LC16 DOUT29
| | | | | | +--- LC14 DOUT30
| | | | | | | +- LC11 DOUT31
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