📄 reg32b.rpt
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Device-Specific Information: d:\vhdl\work5 freqtest\reg32b.rpt
reg32b
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC64 DOUT0
| +----------------------------- LC61 DOUT1
| | +--------------------------- LC58 DOUT2
| | | +------------------------- LC56 DOUT3
| | | | +----------------------- LC60 DOUT4
| | | | | +--------------------- LC55 DOUT5
| | | | | | +------------------- LC57 DOUT6
| | | | | | | +----------------- LC59 DOUT7
| | | | | | | | +--------------- LC54 DOUT8
| | | | | | | | | +------------- LC62 DOUT9
| | | | | | | | | | +----------- LC63 DOUT10
| | | | | | | | | | | +--------- LC53 DOUT11
| | | | | | | | | | | | +------- LC52 DOUT12
| | | | | | | | | | | | | +----- LC51 DOUT13
| | | | | | | | | | | | | | +--- LC50 DOUT14
| | | | | | | | | | | | | | | +- LC49 DOUT15
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
Pin
5 -> * - - - - - - - - - - - - - - - | - - - * | <-- DIN0
35 -> - * - - - - - - - - - - - - - - | - - - * | <-- DIN1
31 -> - - * - - - - - - - - - - - - - | - - - * | <-- DIN2
30 -> - - - * - - - - - - - - - - - - | - - - * | <-- DIN3
27 -> - - - - * - - - - - - - - - - - | - - - * | <-- DIN4
25 -> - - - - - * - - - - - - - - - - | - - - * | <-- DIN5
41 -> - - - - - - * - - - - - - - - - | - - - * | <-- DIN6
39 -> - - - - - - - * - - - - - - - - | - - - * | <-- DIN7
37 -> - - - - - - - - * - - - - - - - | - - - * | <-- DIN8
36 -> - - - - - - - - - * - - - - - - | - - - * | <-- DIN9
24 -> - - - - - - - - - - * - - - - - | - - - * | <-- DIN10
28 -> - - - - - - - - - - - * - - - - | - - - * | <-- DIN11
29 -> - - - - - - - - - - - - * - - - | - - - * | <-- DIN12
33 -> - - - - - - - - - - - - - * - - | - - - * | <-- DIN13
34 -> - - - - - - - - - - - - - - * - | - - - * | <-- DIN14
23 -> - - - - - - - - - - - - - - - * | - - - * | <-- DIN15
83 -> - - - - - - - - - - - - - - - - | - - - - | <-- LK
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\work5 freqtest\reg32b.rpt
reg32b
** EQUATIONS **
DIN0 : INPUT;
DIN1 : INPUT;
DIN2 : INPUT;
DIN3 : INPUT;
DIN4 : INPUT;
DIN5 : INPUT;
DIN6 : INPUT;
DIN7 : INPUT;
DIN8 : INPUT;
DIN9 : INPUT;
DIN10 : INPUT;
DIN11 : INPUT;
DIN12 : INPUT;
DIN13 : INPUT;
DIN14 : INPUT;
DIN15 : INPUT;
DIN16 : INPUT;
DIN17 : INPUT;
DIN18 : INPUT;
DIN19 : INPUT;
DIN20 : INPUT;
DIN21 : INPUT;
DIN22 : INPUT;
DIN23 : INPUT;
DIN24 : INPUT;
DIN25 : INPUT;
DIN26 : INPUT;
DIN27 : INPUT;
DIN28 : INPUT;
DIN29 : INPUT;
DIN30 : INPUT;
DIN31 : INPUT;
LK : INPUT;
-- Node name is 'DOUT0' = ':96'
-- Equation name is 'DOUT0', type is output
DOUT0 = DFFE( DIN0 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT1' = ':94'
-- Equation name is 'DOUT1', type is output
DOUT1 = DFFE( DIN1 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT2' = ':92'
-- Equation name is 'DOUT2', type is output
DOUT2 = DFFE( DIN2 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT3' = ':90'
-- Equation name is 'DOUT3', type is output
DOUT3 = DFFE( DIN3 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT4' = ':88'
-- Equation name is 'DOUT4', type is output
DOUT4 = DFFE( DIN4 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT5' = ':86'
-- Equation name is 'DOUT5', type is output
DOUT5 = DFFE( DIN5 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT6' = ':84'
-- Equation name is 'DOUT6', type is output
DOUT6 = DFFE( DIN6 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT7' = ':82'
-- Equation name is 'DOUT7', type is output
DOUT7 = DFFE( DIN7 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT8' = ':80'
-- Equation name is 'DOUT8', type is output
DOUT8 = DFFE( DIN8 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT9' = ':78'
-- Equation name is 'DOUT9', type is output
DOUT9 = DFFE( DIN9 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT10' = ':76'
-- Equation name is 'DOUT10', type is output
DOUT10 = DFFE( DIN10 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT11' = ':74'
-- Equation name is 'DOUT11', type is output
DOUT11 = DFFE( DIN11 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT12' = ':72'
-- Equation name is 'DOUT12', type is output
DOUT12 = DFFE( DIN12 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT13' = ':70'
-- Equation name is 'DOUT13', type is output
DOUT13 = DFFE( DIN13 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT14' = ':68'
-- Equation name is 'DOUT14', type is output
DOUT14 = DFFE( DIN14 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT15' = ':66'
-- Equation name is 'DOUT15', type is output
DOUT15 = DFFE( DIN15 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT16' = ':64'
-- Equation name is 'DOUT16', type is output
DOUT16 = DFFE( DIN16 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT17' = ':62'
-- Equation name is 'DOUT17', type is output
DOUT17 = DFFE( DIN17 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT18' = ':60'
-- Equation name is 'DOUT18', type is output
DOUT18 = DFFE( DIN18 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT19' = ':58'
-- Equation name is 'DOUT19', type is output
DOUT19 = DFFE( DIN19 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT20' = ':56'
-- Equation name is 'DOUT20', type is output
DOUT20 = DFFE( DIN20 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT21' = ':54'
-- Equation name is 'DOUT21', type is output
DOUT21 = DFFE( DIN21 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT22' = ':52'
-- Equation name is 'DOUT22', type is output
DOUT22 = DFFE( DIN22 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT23' = ':50'
-- Equation name is 'DOUT23', type is output
DOUT23 = DFFE( DIN23 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT24' = ':48'
-- Equation name is 'DOUT24', type is output
DOUT24 = DFFE( DIN24 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT25' = ':46'
-- Equation name is 'DOUT25', type is output
DOUT25 = DFFE( DIN25 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT26' = ':44'
-- Equation name is 'DOUT26', type is output
DOUT26 = DFFE( DIN26 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT27' = ':42'
-- Equation name is 'DOUT27', type is output
DOUT27 = DFFE( DIN27 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT28' = ':40'
-- Equation name is 'DOUT28', type is output
DOUT28 = DFFE( DIN28 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT29' = ':38'
-- Equation name is 'DOUT29', type is output
DOUT29 = DFFE( DIN29 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT30' = ':36'
-- Equation name is 'DOUT30', type is output
DOUT30 = DFFE( DIN30 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Node name is 'DOUT31' = ':34'
-- Equation name is 'DOUT31', type is output
DOUT31 = DFFE( DIN31 $ GND, GLOBAL( LK), VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl\work5 freqtest\reg32b.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,967K
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