📄 reg32b.rpt
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Project Information d:\vhdl\work5 freqtest\reg32b.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/21/2008 09:30:48
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
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net list, support information, device programming or simulation file, or
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***** Project compilation was successful
REG32B
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
reg32b EPM7064LC84-7 33 32 0 32 0 50 %
User Pins: 33 32 0
Project Information d:\vhdl\work5 freqtest\reg32b.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'LK' chosen for auto global Clock
Device-Specific Information: d:\vhdl\work5 freqtest\reg32b.rpt
reg32b
***** Logic for device 'reg32b' compiled without errors.
Device: EPM7064LC84-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: d:\vhdl\work5 freqtest\reg32b.rpt
reg32b
** ERROR SUMMARY **
Info: Chip 'reg32b' in device 'EPM7064LC84-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
V D
D D D D D D C D O D V D D D
I I I I I D I C O U O C O O O
N N N N G N I N I G G G G U T U C U U U
2 2 2 3 N 3 N 1 N N N N L N T 1 T I T T T
7 8 9 0 D 1 0 7 T D D D K D 0 0 9 O 1 4 7
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
DIN26 | 12 74 | DOUT2
VCCIO | 13 73 | DOUT6
DIN25 | 14 72 | GND
DIN24 | 15 71 | DOUT3
DIN23 | 16 70 | DOUT5
DIN22 | 17 69 | DOUT8
DIN21 | 18 68 | DOUT11
GND | 19 67 | DOUT12
DIN20 | 20 66 | VCCIO
DIN19 | 21 65 | DOUT13
DIN18 | 22 EPM7064LC84-7 64 | DOUT14
DIN15 | 23 63 | DOUT15
DIN10 | 24 62 | DOUT23
DIN5 | 25 61 | DOUT24
VCCIO | 26 60 | DOUT25
DIN4 | 27 59 | GND
DIN11 | 28 58 | DOUT26
DIN12 | 29 57 | DOUT27
DIN3 | 30 56 | DOUT28
DIN2 | 31 55 | DOUT29
GND | 32 54 | DOUT30
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
D D D D D V D D D G V D D D G D D D D D V
I I I I I C I I I N C O O O N O O O O O C
N N N N N C N N N D C U U U D U U U U U C
1 1 1 9 8 I 7 1 6 I T T T T T T T T I
3 4 O 6 N 1 1 1 1 2 2 2 3 O
T 9 8 7 6 0 1 2 1
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\vhdl\work5 freqtest\reg32b.rpt
reg32b
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 16/16(100%) 16/16(100%) 0/16( 0%) 16/36( 44%)
D: LC49 - LC64 16/16(100%) 16/16(100%) 0/16( 0%) 16/36( 44%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 64/64 (100%)
Total logic cells used: 32/64 ( 50%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 32/64 ( 50%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 2.00
Total fan-in: 64
Total input pins required: 33
Total output pins required: 32
Total bidirectional pins required: 0
Total logic cells required: 32
Total flipflops required: 32
Total product terms required: 32
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: d:\vhdl\work5 freqtest\reg32b.rpt
reg32b
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
5 (15) (A) INPUT 0 0 0 0 0 1 0 DIN0
35 (22) (B) INPUT 0 0 0 0 0 1 0 DIN1
31 (25) (B) INPUT 0 0 0 0 0 1 0 DIN2
30 (26) (B) INPUT 0 0 0 0 0 1 0 DIN3
27 (29) (B) INPUT 0 0 0 0 0 1 0 DIN4
25 (30) (B) INPUT 0 0 0 0 0 1 0 DIN5
41 (17) (B) INPUT 0 0 0 0 0 1 0 DIN6
39 (19) (B) INPUT 0 0 0 0 0 1 0 DIN7
37 (20) (B) INPUT 0 0 0 0 0 1 0 DIN8
36 (21) (B) INPUT 0 0 0 0 0 1 0 DIN9
24 (31) (B) INPUT 0 0 0 0 0 1 0 DIN10
28 (28) (B) INPUT 0 0 0 0 0 1 0 DIN11
29 (27) (B) INPUT 0 0 0 0 0 1 0 DIN12
33 (24) (B) INPUT 0 0 0 0 0 1 0 DIN13
34 (23) (B) INPUT 0 0 0 0 0 1 0 DIN14
23 (32) (B) INPUT 0 0 0 0 0 1 0 DIN15
40 (18) (B) INPUT 0 0 0 0 0 1 0 DIN16
4 (16) (A) INPUT 0 0 0 0 0 1 0 DIN17
22 (1) (A) INPUT 0 0 0 0 0 1 0 DIN18
21 (2) (A) INPUT 0 0 0 0 0 1 0 DIN19
20 (3) (A) INPUT 0 0 0 0 0 1 0 DIN20
18 (4) (A) INPUT 0 0 0 0 0 1 0 DIN21
17 (5) (A) INPUT 0 0 0 0 0 1 0 DIN22
16 (6) (A) INPUT 0 0 0 0 0 1 0 DIN23
15 (7) (A) INPUT 0 0 0 0 0 1 0 DIN24
14 (8) (A) INPUT 0 0 0 0 0 1 0 DIN25
12 (9) (A) INPUT 0 0 0 0 0 1 0 DIN26
11 (10) (A) INPUT 0 0 0 0 0 1 0 DIN27
10 (11) (A) INPUT 0 0 0 0 0 1 0 DIN28
9 (12) (A) INPUT 0 0 0 0 0 1 0 DIN29
8 (13) (A) INPUT 0 0 0 0 0 1 0 DIN30
6 (14) (A) INPUT 0 0 0 0 0 1 0 DIN31
83 - - INPUT G 0 0 0 0 0 0 0 LK
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\vhdl\work5 freqtest\reg32b.rpt
reg32b
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
81 64 D FF + t 0 0 0 1 0 0 0 DOUT0
77 61 D FF + t 0 0 0 1 0 0 0 DOUT1
74 58 D FF + t 0 0 0 1 0 0 0 DOUT2
71 56 D FF + t 0 0 0 1 0 0 0 DOUT3
76 60 D FF + t 0 0 0 1 0 0 0 DOUT4
70 55 D FF + t 0 0 0 1 0 0 0 DOUT5
73 57 D FF + t 0 0 0 1 0 0 0 DOUT6
75 59 D FF + t 0 0 0 1 0 0 0 DOUT7
69 54 D FF + t 0 0 0 1 0 0 0 DOUT8
79 62 D FF + t 0 0 0 1 0 0 0 DOUT9
80 63 D FF + t 0 0 0 1 0 0 0 DOUT10
68 53 D FF + t 0 0 0 1 0 0 0 DOUT11
67 52 D FF + t 0 0 0 1 0 0 0 DOUT12
65 51 D FF + t 0 0 0 1 0 0 0 DOUT13
64 50 D FF + t 0 0 0 1 0 0 0 DOUT14
63 49 D FF + t 0 0 0 1 0 0 0 DOUT15
48 36 C FF + t 0 0 0 1 0 0 0 DOUT16
46 35 C FF + t 0 0 0 1 0 0 0 DOUT17
45 34 C FF + t 0 0 0 1 0 0 0 DOUT18
44 33 C FF + t 0 0 0 1 0 0 0 DOUT19
49 37 C FF + t 0 0 0 1 0 0 0 DOUT20
50 38 C FF + t 0 0 0 1 0 0 0 DOUT21
51 39 C FF + t 0 0 0 1 0 0 0 DOUT22
62 48 C FF + t 0 0 0 1 0 0 0 DOUT23
61 47 C FF + t 0 0 0 1 0 0 0 DOUT24
60 46 C FF + t 0 0 0 1 0 0 0 DOUT25
58 45 C FF + t 0 0 0 1 0 0 0 DOUT26
57 44 C FF + t 0 0 0 1 0 0 0 DOUT27
56 43 C FF + t 0 0 0 1 0 0 0 DOUT28
55 42 C FF + t 0 0 0 1 0 0 0 DOUT29
54 41 C FF + t 0 0 0 1 0 0 0 DOUT30
52 40 C FF + t 0 0 0 1 0 0 0 DOUT31
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\work5 freqtest\reg32b.rpt
reg32b
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC36 DOUT16
| +----------------------------- LC35 DOUT17
| | +--------------------------- LC34 DOUT18
| | | +------------------------- LC33 DOUT19
| | | | +----------------------- LC37 DOUT20
| | | | | +--------------------- LC38 DOUT21
| | | | | | +------------------- LC39 DOUT22
| | | | | | | +----------------- LC48 DOUT23
| | | | | | | | +--------------- LC47 DOUT24
| | | | | | | | | +------------- LC46 DOUT25
| | | | | | | | | | +----------- LC45 DOUT26
| | | | | | | | | | | +--------- LC44 DOUT27
| | | | | | | | | | | | +------- LC43 DOUT28
| | | | | | | | | | | | | +----- LC42 DOUT29
| | | | | | | | | | | | | | +--- LC41 DOUT30
| | | | | | | | | | | | | | | +- LC40 DOUT31
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
Pin
40 -> * - - - - - - - - - - - - - - - | - - * - | <-- DIN16
4 -> - * - - - - - - - - - - - - - - | - - * - | <-- DIN17
22 -> - - * - - - - - - - - - - - - - | - - * - | <-- DIN18
21 -> - - - * - - - - - - - - - - - - | - - * - | <-- DIN19
20 -> - - - - * - - - - - - - - - - - | - - * - | <-- DIN20
18 -> - - - - - * - - - - - - - - - - | - - * - | <-- DIN21
17 -> - - - - - - * - - - - - - - - - | - - * - | <-- DIN22
16 -> - - - - - - - * - - - - - - - - | - - * - | <-- DIN23
15 -> - - - - - - - - * - - - - - - - | - - * - | <-- DIN24
14 -> - - - - - - - - - * - - - - - - | - - * - | <-- DIN25
12 -> - - - - - - - - - - * - - - - - | - - * - | <-- DIN26
11 -> - - - - - - - - - - - * - - - - | - - * - | <-- DIN27
10 -> - - - - - - - - - - - - * - - - | - - * - | <-- DIN28
9 -> - - - - - - - - - - - - - * - - | - - * - | <-- DIN29
8 -> - - - - - - - - - - - - - - * - | - - * - | <-- DIN30
6 -> - - - - - - - - - - - - - - - * | - - * - | <-- DIN31
83 -> - - - - - - - - - - - - - - - - | - - - - | <-- LK
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
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