📄 freqtest.rpt
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Project Information d:\vhdl\work5 freqtest\freqtest.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/23/2008 17:45:06
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
FREQTEST
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
freqtest EPM7096LC68-7 2 32 0 78 0 81 %
User Pins: 2 32 0
Project Information d:\vhdl\work5 freqtest\freqtest.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'FSIN' chosen for auto global Clock
Project Information d:\vhdl\work5 freqtest\freqtest.rpt
** FILE HIERARCHY **
|ftctrl:U1|
|reg32b:U2|
|counter32b:U3|
|counter32b:U3|lpm_add_sub:298|
|counter32b:U3|lpm_add_sub:298|addcore:adder|
|counter32b:U3|lpm_add_sub:298|addcore:adder|addcore:adder3|
|counter32b:U3|lpm_add_sub:298|addcore:adder|addcore:adder2|
|counter32b:U3|lpm_add_sub:298|addcore:adder|addcore:adder1|
|counter32b:U3|lpm_add_sub:298|addcore:adder|addcore:adder0|
|counter32b:U3|lpm_add_sub:298|altshift:result_ext_latency_ffs|
|counter32b:U3|lpm_add_sub:298|altshift:carry_ext_latency_ffs|
|counter32b:U3|lpm_add_sub:298|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\vhdl\work5 freqtest\freqtest.rpt
freqtest
***** Logic for device 'freqtest' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
R R R R R R R
E E E E E E E
S S S S S V S S D D
E E E E E C E E V O O
R R R R R C F R R C U U
V V V G V V I G G G S G V V C T T
E E E N E E N N N N I N E E I 2 2
D D D D D D T D D D N D D D O 4 5
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
RESERVED | 10 60 | DOUT26
VCCIO | 11 59 | DOUT27
RESERVED | 12 58 | GND
CLK1Hz | 13 57 | DOUT28
DOUT30 | 14 56 | DOUT31
DOUT13 | 15 55 | DOUT8
GND | 16 54 | DOUT9
DOUT14 | 17 53 | VCCIO
RESERVED | 18 EPM7096LC68-7 52 | DOUT10
DOUT7 | 19 51 | RESERVED
DOUT15 | 20 50 | DOUT11
VCCIO | 21 49 | RESERVED
DOUT23 | 22 48 | GND
DOUT29 | 23 47 | DOUT12
DOUT4 | 24 46 | RESERVED
DOUT3 | 25 45 | DOUT16
GND | 26 44 | DOUT17
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
R D D D V D D G V D D G D D R D V
E O O O C O O N C O O N O O E O C
S U U U C U U D C U U D U U S U C
E T T T I T T I T T T T E T I
R 6 2 1 O 0 5 N 2 2 2 1 R 1 O
V T 0 1 2 9 V 8
E E
D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\vhdl\work5 freqtest\freqtest.rpt
freqtest
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 14/16( 87%) 7/ 8( 87%) 0/16( 0%) 16/36( 44%)
C: LC33 - LC48 16/16(100%) 7/ 8( 87%) 0/16( 0%) 11/36( 30%)
D: LC49 - LC64 16/16(100%) 7/ 8( 87%) 0/16( 0%) 12/36( 33%)
E: LC65 - LC80 16/16(100%) 5/ 8( 62%) 0/16( 0%) 18/36( 50%)
F: LC81 - LC96 16/16(100%) 6/ 8( 75%) 0/16( 0%) 20/36( 55%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 33/48 ( 68%)
Total logic cells used: 78/96 ( 81%)
Total shareable expanders used: 0/96 ( 0%)
Total Turbo logic cells used: 78/96 ( 81%)
Total shareable expanders not available (n/a): 0/96 ( 0%)
Average fan-in: 6.47
Total fan-in: 505
Total input pins required: 2
Total output pins required: 32
Total bidirectional pins required: 0
Total logic cells required: 78
Total flipflops required: 65
Total product terms required: 167
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 96 ( 0%)
Device-Specific Information: d:\vhdl\work5 freqtest\freqtest.rpt
freqtest
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
13 (1) (A) INPUT 0 0 0 0 0 0 33 CLK1Hz
67 - - INPUT G 0 0 0 0 0 0 0 FSIN
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\vhdl\work5 freqtest\freqtest.rpt
freqtest
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
32 35 C FF t 0 0 0 0 2 0 0 DOUT0
30 37 C FF t 0 0 0 0 2 0 0 DOUT1
29 40 C FF t 0 0 0 0 2 0 0 DOUT2
25 45 C FF t 0 0 0 0 2 0 0 DOUT3
24 48 C FF t 0 0 0 0 2 0 0 DOUT4
33 33 C FF t 0 0 0 0 2 0 0 DOUT5
28 41 C FF t 0 0 0 0 2 0 0 DOUT6
19 24 B FF t 0 0 0 0 2 0 0 DOUT7
55 80 E FF t 0 0 0 0 2 0 0 DOUT8
54 77 E FF t 0 0 0 0 2 0 0 DOUT9
52 75 E FF t 0 0 0 0 2 0 0 DOUT10
50 72 E FF t 0 0 0 0 2 0 0 DOUT11
47 67 E FF t 0 0 0 0 2 0 0 DOUT12
15 29 B FF t 0 0 0 0 2 0 0 DOUT13
17 27 B FF t 0 0 0 0 2 0 0 DOUT14
20 21 B FF t 0 0 0 0 2 0 0 DOUT15
45 64 D FF t 0 0 0 0 2 0 0 DOUT16
44 61 D FF t 0 0 0 0 2 0 0 DOUT17
42 59 D FF t 0 0 0 0 2 0 0 DOUT18
40 56 D FF t 0 0 0 0 2 0 0 DOUT19
36 49 D FF t 0 0 0 0 2 0 0 DOUT20
37 51 D FF t 0 0 0 0 2 0 0 DOUT21
39 53 D FF t 0 0 0 0 2 0 0 DOUT22
22 19 B FF t 0 0 0 0 2 0 0 DOUT23
62 92 F FF t 0 0 0 0 2 0 0 DOUT24
61 89 F FF t 0 0 0 0 2 0 0 DOUT25
60 88 F FF t 0 0 0 0 2 0 0 DOUT26
59 86 F FF t 0 0 0 0 2 0 0 DOUT27
57 84 F FF t 0 0 0 0 2 0 0 DOUT28
23 17 B FF t 0 0 0 0 2 0 0 DOUT29
14 32 B FF t 0 0 0 0 2 0 0 DOUT30
56 81 F FF t 0 0 0 0 2 0 0 DOUT31
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\work5 freqtest\freqtest.rpt
freqtest
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 34 C SOFT t 0 0 0 0 6 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node5
- 36 C SOFT t 0 0 0 0 7 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node6
- 79 E SOFT t 0 0 0 0 8 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder0|result_node7
(51) 73 E SOFT t 0 0 0 0 16 0 15 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder1|cout_node
- 78 E SOFT t 0 0 0 0 14 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node5
- 76 E SOFT t 0 0 0 0 15 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node6
- 74 E SOFT t 0 0 0 0 16 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder1|result_node7
- 63 D SOFT t 0 0 0 0 7 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node5
- 62 D SOFT t 0 0 0 0 8 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node6
- 87 F SOFT t 0 0 0 0 9 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder2|result_node7
- 85 F SOFT t 0 0 0 0 15 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node5
- 82 F SOFT t 0 0 0 0 16 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node6
(65) 96 F SOFT t 0 0 0 0 17 0 1 |COUNTER32B:U3|LPM_ADD_SUB:298|addcore:adder|addcore:adder3|result_node7
(64) 94 F DFFE + t 0 0 0 1 3 1 2 |COUNTER32B:U3|CQI31 (|COUNTER32B:U3|:36)
- 26 B DFFE + t 0 0 0 1 3 1 3 |COUNTER32B:U3|CQI30 (|COUNTER32B:U3|:37)
(18) 25 B DFFE + t 0 0 0 1 3 1 4 |COUNTER32B:U3|CQI29 (|COUNTER32B:U3|:38)
- 91 F TFFE + t 0 0 0 1 14 1 3 |COUNTER32B:U3|CQI28 (|COUNTER32B:U3|:39)
- 83 F TFFE + t 0 0 0 1 13 1 4 |COUNTER32B:U3|CQI27 (|COUNTER32B:U3|:40)
- 90 F TFFE + t 0 0 0 1 12 1 5 |COUNTER32B:U3|CQI26 (|COUNTER32B:U3|:41)
- 93 F TFFE + t 0 0 0 1 11 1 6 |COUNTER32B:U3|CQI25 (|COUNTER32B:U3|:42)
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