cnt10.vhd

设计含异步清零和同步时钟使能的加法计数器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
  PORT (CLK,RST,EN : IN STD_LOGIC;
                CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
              COUT : OUT STD_LOGIC);
END CNT10;
ARCHITECTURE behav OF CNT10 IS    -- 结构体名和实体名可以不一样
BEGIN 
  PROCESS(CLK,RST,EN)
    VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); 
BEGIN
     IF RST = '1' THEN CQI := (OTHERS =>'0');  --异步复位端
      ELSIF CLK'EVENT AND CLK='1' THEN        --时钟上升沿有