lcd_v.tan.qmsg

FPGA实现的LCD接口

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[0\] register sld_hub:sld_hub_inst\|hub_tdo 95.2 MHz 10.504 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 95.2 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 10.504 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.998 ns + Longest register register " "Info: + Longest register to register delay is 4.998 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[0\] 1 REG LCFF_X42_Y18_N23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y18_N23; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[0\]'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.916 ns) + CELL(0.664 ns) 2.580 ns sld_hub:sld_hub_inst\|hub_tdo~279 2 COMB LCCOMB_X36_Y19_N30 1 " "Info: 2: + IC(1.916 ns) + CELL(0.664 ns) = 2.580 ns; Loc. = LCCOMB_X36_Y19_N30; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~279'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "2.580 ns" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] sld_hub:sld_hub_inst|hub_tdo~279 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.210 ns) 3.155 ns sld_hub:sld_hub_inst\|hub_tdo~280 3 COMB LCCOMB_X36_Y19_N22 1 " "Info: 3: + IC(0.365 ns) + CELL(0.210 ns) = 3.155 ns; Loc. = LCCOMB_X36_Y19_N22; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~280'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.575 ns" { sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.097 ns) + CELL(0.636 ns) 4.888 ns sld_hub:sld_hub_inst\|hub_tdo~283 4 COMB LCCOMB_X32_Y19_N2 1 " "Info: 4: + IC(1.097 ns) + CELL(0.636 ns) = 4.888 ns; Loc. = LCCOMB_X32_Y19_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~283'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.733 ns" { sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo~283 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 4.998 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LCFF_X32_Y19_N3 1 " "Info: 5: + IC(0.000 ns) + CELL(0.110 ns) = 4.998 ns; Loc. = LCFF_X32_Y19_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.110 ns" { sld_hub:sld_hub_inst|hub_tdo~283 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.620 ns 32.41 % " "Info: Total cell delay = 1.620 ns ( 32.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.378 ns 67.59 % " "Info: Total interconnect delay = 3.378 ns ( 67.59 % )" {  } {  } 0}  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "4.998 ns" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo~283 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.998 ns" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo~283 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.916ns 0.365ns 1.097ns 0.000ns } { 0.000ns 0.664ns 0.210ns 0.636ns 0.110ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.016 ns - Smallest " "Info: - Smallest clock skew is 0.016 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 1.906 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 1.906 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 306 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G3; Fanout = 306; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.227 ns) + CELL(0.679 ns) 1.906 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LCFF_X32_Y19_N3 1 " "Info: 3: + IC(1.227 ns) + CELL(0.679 ns) = 1.906 ns; Loc. = LCFF_X32_Y19_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.906 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 35.62 % " "Info: Total cell delay = 0.679 ns ( 35.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.227 ns 64.38 % " "Info: Total interconnect delay = 1.227 ns ( 64.38 % )" {  } {  } 0}  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.227ns } { 0.000ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 1.890 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 1.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 306 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G3; Fanout = 306; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.679 ns) 1.890 ns sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[0\] 3 REG LCFF_X42_Y18_N23 1 " "Info: 3: + IC(1.211 ns) + CELL(0.679 ns) = 1.890 ns; Loc. = LCFF_X42_Y18_N23; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[0\]'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.890 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 35.93 % " "Info: Total cell delay = 0.679 ns ( 35.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.211 ns 64.07 % " "Info: Total interconnect delay = 1.211 ns ( 64.07 % )" {  } {  } 0}  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.890 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.890 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] } { 0.000ns 0.000ns 1.211ns } { 0.000ns 0.000ns 0.679ns } } }  } 0}  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.227ns } { 0.000ns 0.000ns 0.679ns } } } { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.890 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.890 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] } { 0.000ns 0.000ns 1.211ns } { 0.000ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "4.998 ns" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo~283 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.998 ns" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo~283 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.916ns 0.365ns 1.097ns 0.000ns } { 0.000ns 0.664ns 0.210ns 0.636ns 0.110ns } } } { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.906 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.227ns } { 0.000ns 0.000ns 0.679ns } } } { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.890 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.890 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] } { 0.000ns 0.000ns 1.211ns } { 0.000ns 0.000ns 0.679ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "mclk 12 " "Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock \"mclk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}