lcd_v.tan.qmsg

来自「FPGA实现的LCD接口」· QMSG 代码 · 共 9 行 · 第 1/5 页

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off lcd_v -c lcd_v --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lcd_v -c lcd_v --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "mclk " "Info: Assuming node \"mclk\" is an undefined clock" {  } { { "lcd_v.bdf" "" { Schematic "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mclk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}