lcd_v.fit.summary

来自「FPGA实现的LCD接口」· SUMMARY 代码 · 共 16 行

Flow Status : Successful - Sun Feb 11 23:29:04 2007
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : lcd_v
Top-level Entity Name : lcd_v
Family : Cyclone II
Device : EP2C35F484C8
Timing Models : Preliminary
Met timing requirements : N/A
Total logic elements : 454 / 33,216 ( 1 % )
Total registers : 373
Total pins : 13 / 322 ( 4 % )
Total virtual pins : 0
Total memory bits : 34,816 / 483,840 ( 7 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )