lcd_v.tan.qmsg

FPGA实现的LCD接口

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "23 " "Warning: Found 23 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clk_int " "Info: Detected ripple clock \"lcd:inst1\|clk_int\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 91 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clk_int" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "div16:inst\|count\[3\] " "Info: Detected ripple clock \"div16:inst\|count\[3\]\" as buffer" {  } { { "DIV16.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/DIV16.v" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div16:inst\|count\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[3\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[3\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[2\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[2\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[0\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[0\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[1\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[1\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[7\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[7\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[7\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[4\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[4\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[4\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[5\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[5\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[5\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[6\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[6\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[6\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[12\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[12\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[12\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[14\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[14\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[14\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[15\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[15\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[15\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[13\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[13\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[13\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[11\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[11\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[11\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[10\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[10\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[10\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[9\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[9\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[9\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[8\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[8\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[8\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst1\|reduce_nor~127 " "Info: Detected gated clock \"lcd:inst1\|reduce_nor~127\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|reduce_nor~127" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst1\|reduce_nor~128 " "Info: Detected gated clock \"lcd:inst1\|reduce_nor~128\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|reduce_nor~128" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst1\|reduce_nor~130 " "Info: Detected gated clock \"lcd:inst1\|reduce_nor~130\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|reduce_nor~130" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst1\|reduce_nor~129 " "Info: Detected gated clock \"lcd:inst1\|reduce_nor~129\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|reduce_nor~129" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkdiv " "Info: Detected ripple clock \"lcd:inst1\|clkdiv\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 84 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkdiv" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "mclk register lcd:inst1\|lcd_e register sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\] 56.58 MHz 17.674 ns Internal " "Info: Clock \"mclk\" has Internal fmax of 56.58 MHz between source register \"lcd:inst1\|lcd_e\" and destination register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\]\" (period= 17.674 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.892 ns + Longest register register " "Info: + Longest register to register delay is 0.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst1\|lcd_e 1 REG LCFF_X40_Y19_N25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y19_N25; Fanout = 3; REG Node = 'lcd:inst1\|lcd_e'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.469 ns) 0.892 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\] 2 REG LCFF_X40_Y19_N21 5 " "Info: 2: + IC(0.423 ns) + CELL(0.469 ns) = 0.892 ns; Loc. = LCFF_X40_Y19_N21; Fanout = 5; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\]'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.892 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.469 ns 52.58 % " "Info: Total cell delay = 0.469 ns ( 52.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.423 ns 47.42 % " "Info: Total interconnect delay = 0.423 ns ( 47.42 % )" {  } {  } 0}  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.892 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.892 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } { 0.000ns 0.423ns } { 0.000ns 0.469ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-7.675 ns - Smallest " "Info: - Smallest clock skew is -7.675 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 6.113 ns + Shortest register " "Info: + Shortest clock path from clock \"mclk\" to destination register is 6.113 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns mclk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'mclk'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.232 ns mclk~clkctrl 2 COMB CLKCTRL_G14 4 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.232 ns; Loc. = CLKCTRL_G14; Fanout = 4; COMB Node = 'mclk~clkctrl'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.132 ns" { mclk mclk~clkctrl } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.989 ns) 3.416 ns div16:inst\|count\[3\] 3 REG LCFF_X34_Y2_N5 2 " "Info: 3: + IC(1.195 ns) + CELL(0.989 ns) = 3.416 ns; Loc. = LCFF_X34_Y2_N5; Fanout = 2; REG Node = 'div16:inst\|count\[3\]'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "2.184 ns" { mclk~clkctrl div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/DIV16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.000 ns) 4.239 ns div16:inst\|count\[3\]~clkctrl 4 COMB CLKCTRL_G13 278 " "Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.239 ns; Loc. = CLKCTRL_G13; Fanout = 278; COMB Node = 'div16:inst\|count\[3\]~clkctrl'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.823 ns" { div16:inst|count[3] div16:inst|count[3]~clkctrl } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/DIV16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.679 ns) 6.113 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\] 5 REG LCFF_X40_Y19_N21 5 " "Info: 5: + IC(1.195 ns) + CELL(0.679 ns) = 6.113 ns; Loc. = LCFF_X40_Y19_N21; Fanout = 5; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\]'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.874 ns" { div16:inst|count[3]~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.768 ns 45.28 % " "Info: Total cell delay = 2.768 ns ( 45.28 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.345 ns 54.72 % " "Info: Total interconnect delay = 3.345 ns ( 54.72 % )" {  } {  } 0}  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "6.113 ns" { mclk mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.113 ns" { mclk mclk~combout mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } { 0.000ns 0.000ns 0.132ns 1.195ns 0.823ns 1.195ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 13.788 ns - Longest register " "Info: - Longest clock path from clock \"mclk\" to source register is 13.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns mclk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'mclk'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.232 ns mclk~clkctrl 2 COMB CLKCTRL_G14 4 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.232 ns; Loc. = CLKCTRL_G14; Fanout = 4; COMB Node = 'mclk~clkctrl'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.132 ns" { mclk mclk~clkctrl } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.989 ns) 3.416 ns div16:inst\|count\[3\] 3 REG LCFF_X34_Y2_N5 2 " "Info: 3: + IC(1.195 ns) + CELL(0.989 ns) = 3.416 ns; Loc. = LCFF_X34_Y2_N5; Fanout = 2; REG Node = 'div16:inst\|count\[3\]'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "2.184 ns" { mclk~clkctrl div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/DIV16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.000 ns) 4.239 ns div16:inst\|count\[3\]~clkctrl 4 COMB CLKCTRL_G13 278 " "Info: 4: + IC(0.823 ns) + CELL(0.000 ns) = 4.239 ns; Loc. = CLKCTRL_G13; Fanout = 278; COMB Node = 'div16:inst\|count\[3\]~clkctrl'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.823 ns" { div16:inst|count[3] div16:inst|count[3]~clkctrl } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/DIV16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.989 ns) 6.427 ns lcd:inst1\|clkcnt\[6\] 5 REG LCFF_X54_Y19_N13 3 " "Info: 5: + IC(1.199 ns) + CELL(0.989 ns) = 6.427 ns; Loc. = LCFF_X54_Y19_N13; Fanout = 3; REG Node = 'lcd:inst1\|clkcnt\[6\]'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "2.188 ns" { div16:inst|count[3]~clkctrl lcd:inst1|clkcnt[6] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.168 ns) + CELL(0.664 ns) 8.259 ns lcd:inst1\|reduce_nor~128 6 COMB LCCOMB_X53_Y19_N8 1 " "Info: 6: + IC(1.168 ns) + CELL(0.664 ns) = 8.259 ns; Loc. = LCCOMB_X53_Y19_N8; Fanout = 1; COMB Node = 'lcd:inst1\|reduce_nor~128'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.832 ns" { lcd:inst1|clkcnt[6] lcd:inst1|reduce_nor~128 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.347 ns) + CELL(0.378 ns) 8.984 ns lcd:inst1\|reduce_nor~131 7 COMB LCCOMB_X53_Y19_N4 2 " "Info: 7: + IC(0.347 ns) + CELL(0.378 ns) = 8.984 ns; Loc. = LCCOMB_X53_Y19_N4; Fanout = 2; COMB Node = 'lcd:inst1\|reduce_nor~131'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.725 ns" { lcd:inst1|reduce_nor~128 lcd:inst1|reduce_nor~131 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.346 ns) + CELL(0.989 ns) 10.319 ns lcd:inst1\|clkdiv 8 REG LCFF_X53_Y19_N13 2 " "Info: 8: + IC(0.346 ns) + CELL(0.989 ns) = 10.319 ns; Loc. = LCFF_X53_Y19_N13; Fanout = 2; REG Node = 'lcd:inst1\|clkdiv'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.335 ns" { lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 84 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.597 ns) + CELL(0.000 ns) 11.916 ns lcd:inst1\|clkdiv~clkctrl 9 COMB CLKCTRL_G7 2 " "Info: 9: + IC(1.597 ns) + CELL(0.000 ns) = 11.916 ns; Loc. = CLKCTRL_G7; Fanout = 2; COMB Node = 'lcd:inst1\|clkdiv~clkctrl'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.597 ns" { lcd:inst1|clkdiv lcd:inst1|clkdiv~clkctrl } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 84 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.193 ns) + CELL(0.679 ns) 13.788 ns lcd:inst1\|lcd_e 10 REG LCFF_X40_Y19_N25 3 " "Info: 10: + IC(1.193 ns) + CELL(0.679 ns) = 13.788 ns; Loc. = LCFF_X40_Y19_N25; Fanout = 3; REG Node = 'lcd:inst1\|lcd_e'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "1.872 ns" { lcd:inst1|clkdiv~clkctrl lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.788 ns 41.98 % " "Info: Total cell delay = 5.788 ns ( 41.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.000 ns 58.02 % " "Info: Total interconnect delay = 8.000 ns ( 58.02 % )" {  } {  } 0}  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "13.788 ns" { mclk mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl lcd:inst1|clkcnt[6] lcd:inst1|reduce_nor~128 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clkdiv~clkctrl lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.788 ns" { mclk mclk~combout mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl lcd:inst1|clkcnt[6] lcd:inst1|reduce_nor~128 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clkdiv~clkctrl lcd:inst1|lcd_e } { 0.000ns 0.000ns 0.132ns 1.195ns 0.823ns 1.199ns 1.168ns 0.347ns 0.346ns 1.597ns 1.193ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.664ns 0.378ns 0.989ns 0.000ns 0.679ns } } }  } 0}  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "6.113 ns" { mclk mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.113 ns" { mclk mclk~combout mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } { 0.000ns 0.000ns 0.132ns 1.195ns 0.823ns 1.195ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.679ns } } } { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "13.788 ns" { mclk mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl lcd:inst1|clkcnt[6] lcd:inst1|reduce_nor~128 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clkdiv~clkctrl lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.788 ns" { mclk mclk~combout mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl lcd:inst1|clkcnt[6] lcd:inst1|reduce_nor~128 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clkdiv~clkctrl lcd:inst1|lcd_e } { 0.000ns 0.000ns 0.132ns 1.195ns 0.823ns 1.199ns 1.168ns 0.347ns 0.346ns 1.597ns 1.193ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.664ns 0.378ns 0.989ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 3 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 3 -1 0 } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0}  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.892 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.892 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } { 0.000ns 0.423ns } { 0.000ns 0.469ns } } } { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "6.113 ns" { mclk mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.113 ns" { mclk mclk~combout mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } { 0.000ns 0.000ns 0.132ns 1.195ns 0.823ns 1.195ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.679ns } } } { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "13.788 ns" { mclk mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl lcd:inst1|clkcnt[6] lcd:inst1|reduce_nor~128 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clkdiv~clkctrl lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.788 ns" { mclk mclk~combout mclk~clkctrl div16:inst|count[3] div16:inst|count[3]~clkctrl lcd:inst1|clkcnt[6] lcd:inst1|reduce_nor~128 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clkdiv~clkctrl lcd:inst1|lcd_e } { 0.000ns 0.000ns 0.132ns 1.195ns 0.823ns 1.199ns 1.168ns 0.347ns 0.346ns 1.597ns 1.193ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.664ns 0.378ns 0.989ns 0.000ns 0.679ns } } }  } 0}