count.tan.rpt

一些较为经典的VHDL代码,专注于信号分析与检测方面

+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 8.195 ns   ; plus_1s~reg0 ; plus_1s ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+-------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To            ; To Clock ;
+---------------+-------------+-----------+-------+---------------+----------+
; N/A           ; None        ; -5.148 ns ; reset ; plus_1s~reg0  ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[26] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[24] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[25] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[17] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[18] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[19] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[16] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[21] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[23] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[20] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[22] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[14] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[13] ; clk      ;
; N/A           ; None        ; -5.757 ns ; reset ; count_int[15] ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[7]  ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[4]  ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[5]  ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[6]  ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[9]  ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[10] ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[8]  ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[11] ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[3]  ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[1]  ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[2]  ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[0]  ; clk      ;
; N/A           ; None        ; -6.419 ns ; reset ; count_int[12] ; clk      ;
+---------------+-------------+-----------+-------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Jun 09 20:05:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off count -c count --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 185.36 MHz between source register "count_int[7]" and destination register "count_int[7]" (period= 5.395 ns)
    Info: + Longest register to register delay is 5.131 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y11_N21; Fanout = 3; REG Node = 'count_int[7]'
        Info: 2: + IC(0.481 ns) + CELL(0.651 ns) = 1.132 ns; Loc. = LCCOMB_X16_Y11_N4; Fanout = 1; COMB Node = 'Equal0~284'
        Info: 3: + IC(1.091 ns) + CELL(0.651 ns) = 2.874 ns; Loc. = LCCOMB_X16_Y10_N30; Fanout = 2; COMB Node = 'Equal0~287'
        Info: 4: + IC(0.373 ns) + CELL(0.206 ns) = 3.453 ns; Loc. = LCCOMB_X16_Y10_N28; Fanout = 27; COMB Node = 'count_int[2]~474'
        Info: 5: + IC(1.018 ns) + CELL(0.660 ns) = 5.131 ns; Loc. = LCFF_X16_Y11_N21; Fanout = 3; REG Node = 'count_int[7]'
        Info: Total cell delay = 2.168 ns ( 42.25 % )
        Info: Total interconnect delay = 2.963 ns ( 57.75 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.843 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 28; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.843 ns; Loc. = LCFF_X16_Y11_N21; Fanout = 3; REG Node = 'count_int[7]'
            Info: Total cell delay = 1.806 ns ( 63.52 % )
            Info: Total interconnect delay = 1.037 ns ( 36.48 % )
        Info: - Longest clock path from clock "clk" to source register is 2.843 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 28; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.843 ns; Loc. = LCFF_X16_Y11_N21; Fanout = 3; REG Node = 'count_int[7]'
            Info: Total cell delay = 1.806 ns ( 63.52 % )
            Info: Total interconnect delay = 1.037 ns ( 36.48 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "count_int[7]" (data pin = "reset", clock pin = "clk") is 6.685 ns
    Info: + Longest pin to register delay is 9.568 ns
        Info: 1: + IC(0.000 ns) + CELL(0.954 ns) = 0.954 ns; Loc. = PIN_185; Fanout = 2; PIN Node = 'reset'
        Info: 2: + IC(6.312 ns) + CELL(0.624 ns) = 7.890 ns; Loc. = LCCOMB_X16_Y10_N28; Fanout = 27; COMB Node = 'count_int[2]~474'
        Info: 3: + IC(1.018 ns) + CELL(0.660 ns) = 9.568 ns; Loc. = LCFF_X16_Y11_N21; Fanout = 3; REG Node = 'count_int[7]'
        Info: Total cell delay = 2.238 ns ( 23.39 % )
        Inf