count.vhd

来自「一些较为经典的VHDL代码,专注于信号分析与检测方面」· VHDL 代码 · 共 49 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY count IS
	PORT(
			clk : IN std_logic;
			reset : IN std_logic;
			plus_1s : OUT std_logic
		);
END count;



ARCHITECTURE counter OF count IS
SIGNAL count_int:std_logic_vector(26 downto 0); --std_logic_vector(0 to 26);
BEGIN
	PROCESS--(clk,reset)
	BEGIN
		WAIT UNTIL rising_edge(clk);--if clock event and clk = '1'
		IF reset = '1' THEN
			count_int <= (OTHERS => '0');
			ELSE
				IF(count_int = "11000011010011111") THEN --100000-1
					count_int<=(OTHERS => '0');
				ELSE
					count_int <= count_int + 1;
				END IF;
		END IF;
	END PROCESS;
	
	PROCESS--(clk,reset) 
	BEGIN
		WAIT UNTIL rising_edge(clk);
		IF reset = '1' THEN
			plus_1s <= '0';
			ELSE
				IF(count_int = "11000011010011111") THEN --100000-1
					plus_1s <= '1';
				ELSE
					plus_1s <= '0';
				END IF;
		END IF;
	END PROCESS;	
	
	
END counter;