📄 count.sim.vwf

📁 一些较为经典的VHDL代码,专注于信号分析与检测方面
💻 VWF
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上一页 12
			LEVEL 1 FOR 5120.0;
		}
		LEVEL 0 FOR 5120.0;
		LEVEL 1 FOR 1600.0;
		NODE
		{
			REPEAT = 48;
			LEVEL 0 FOR 5120.0;
			LEVEL 1 FOR 5120.0;
		}
		LEVEL 0 FOR 5120.0;
		LEVEL 1 FOR 3331.853;
	}
}

TRANSITION_LIST("count_int[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10268.147;
		NODE
		{
			REPEAT = 48;
			LEVEL 1 FOR 10240.0;
			LEVEL 0 FOR 10240.0;
		}
		LEVEL 1 FOR 6720.0;
		NODE
		{
			REPEAT = 48;
			LEVEL 0 FOR 10240.0;
			LEVEL 1 FOR 10240.0;
		}
		LEVEL 0 FOR 10240.0;
		LEVEL 1 FOR 6720.0;
		NODE
		{
			REPEAT = 24;
			LEVEL 0 FOR 10240.0;
			LEVEL 1 FOR 10240.0;
		}
		LEVEL 0 FOR 8451.853;
	}
}

TRANSITION_LIST("count_int[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 20508.147;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 23;
				LEVEL 1 FOR 20480.0;
				LEVEL 0 FOR 20480.0;
			}
			LEVEL 1 FOR 20480.0;
			LEVEL 0 FOR 37440.0;
		}
		NODE
		{
			REPEAT = 11;
			LEVEL 1 FOR 20480.0;
			LEVEL 0 FOR 20480.0;
		}
		LEVEL 1 FOR 20480.0;
		LEVEL 0 FOR 8451.853;
	}
}

TRANSITION_LIST("count_int[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 40988.147;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 11;
				LEVEL 1 FOR 40960.0;
				LEVEL 0 FOR 40960.0;
			}
			LEVEL 1 FOR 40960.0;
			LEVEL 0 FOR 57920.0;
		}
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 40960.0;
			LEVEL 0 FOR 40960.0;
		}
		LEVEL 1 FOR 40960.0;
		LEVEL 0 FOR 8451.853;
	}
}

TRANSITION_LIST("count_int[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 81948.125;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 5;
				LEVEL 1 FOR 81920.0;
				LEVEL 0 FOR 81920.0;
			}
			LEVEL 1 FOR 81920.0;
			LEVEL 0 FOR 98880.0;
		}
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 81920.0;
			LEVEL 0 FOR 81920.0;
		}
		LEVEL 1 FOR 81920.0;
		LEVEL 0 FOR 8451.875;
	}
}

TRANSITION_LIST("count_int[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 163868.125;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 2;
				LEVEL 1 FOR 163840.0;
				LEVEL 0 FOR 163840.0;
			}
			LEVEL 1 FOR 163840.0;
			LEVEL 0 FOR 180800.0;
		}
		LEVEL 1 FOR 163840.0;
		LEVEL 0 FOR 163840.0;
		LEVEL 1 FOR 8451.875;
	}
}

TRANSITION_LIST("count_int[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 327708.125;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 327680.0;
			LEVEL 0 FOR 327680.0;
			LEVEL 1 FOR 16960.0;
			LEVEL 0 FOR 327680.0;
		}
		LEVEL 1 FOR 172291.875;
	}
}

TRANSITION_LIST("count_int[16]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 655388.125;
		LEVEL 1 FOR 344640.0;
		LEVEL 0 FOR 655360.0;
		LEVEL 1 FOR 344640.0;
		LEVEL 0 FOR 499971.875;
	}
}

TRANSITION_LIST("count_int[17]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2500000.0;
	}
}

TRANSITION_LIST("count_int[18]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2500000.0;
	}
}

TRANSITION_LIST("count_int[19]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2500000.0;
	}
}

TRANSITION_LIST("count_int[20]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2500000.0;
	}
}

TRANSITION_LIST("count_int[21]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2500000.0;
	}
}

TRANSITION_LIST("count_int[22]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2500000.0;
	}
}

TRANSITION_LIST("count_int[23]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2500000.0;
	}
}

TRANSITION_LIST("count_int[24]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2500000.0;
	}
}

TRANSITION_LIST("count_int[25]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2500000.0;
	}
}

TRANSITION_LIST("count_int[26]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2500000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "count_int";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
	CHILDREN = 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[26]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[25]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[24]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[23]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[22]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[21]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[20]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[19]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[18]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[17]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[16]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 23;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 27;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "count_int[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 28;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "plus_1s";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 29;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "reset";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 30;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 16450;
	MASTER = FALSE;
}

TIME_BAR
{
	TIME = 1000035000;
	MASTER = TRUE;
}

TIME_BAR
{
	TIME = 2000035000;
	MASTER = FALSE;
}
;
上一页 12
💿 文件大小 225 K
👤 上传用户 jiajuncai
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#VHDL #代码 #信号分析 #检测
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