muti_clock.vhd

此为多功能数字电子钟的vhdl代码

library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;


 entity count24 is 
      port(carry: in std_logic;
             rst: in std_logic;
           times: out integer range 0 to 23;
            full: out std_logic);
       end count24;


 architecture arch of count24  is
       signal time: integer range 0 to 23;
 begin 
       process(rst,carry) 
       begin
            if rst='1' then time<=0; full<='0';
            elsif rising_edge(carry) then
                    if time=23 then time<=0;
                                    full<='1';
                    else time<=time+1;
                        full<='0';
                    end if;
             end if;
        end process;
        times<=time;
  end arch;

---------------------------------------  
----alarm_set组件程序
----功能是设置定时
---------------------------------------
 
 library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;


 entity alarm_set is 

    port(rst,hz1: in std_logic;
        alarm,ok: in std_logic;
        sec_tune: in std_logic;
        min_tune: in std_logic;
       hour_tune: in std_logic;
         sec,min: out integer range 0 to 59;
            hour: out integer range 0 to 23);
  end;
 


 architecture arch of alarm_set  is

     signal sec_tmp,min_tmp: integer range 0 to 59;
            signal hour_tmp: integer range 0 to 23;
 begin
   tuning: process(rst,hz1,alarm,ok)
    begin
    if rst='1' then sec_tmp<=0;  min_tmp<=0;  hour_tmp<=0;
    elsif rising_edge(hz1) then 
       if alarm='1' and ok='0' then 
             if sec_tune='1' then
                if sec_tmp=59 then sec_tmp<=0;
                              else sec_tmp<=sec_tmp+1;
                end if;
             end if;
       if min_tune='1' then 
          if min_tmp=59 then min_tmp<=0;
                        else min_tmp<=min_tmp+1;
          end if;
        end if;
      if hour_tune='1' then 
         if hour_tmp=23 then hour_tmp<=0;
                        else hour_tmp<=hour_tmp+1;
         end if;
      end if;
      else 
           null;
      end if;
   end if;
  end process tuning;
      sec<=sec_tmp;
      min<=min_tmp;
      hour<=hour_tmp;
  end arch;

--------------------------------------
--stop_watch组件
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
----定义输入输出
entity stop_watch is
 port(rst,hzl:in std_logic;--系统频率1HZ
      stop:in std_logic;-----定义连续按下设置
      ok:in std_logic;-------确认设置完成
      sec_tune:in std_logic;-----秒设置
      min_tune:in std_logic;-----分设置
      hour_tune:in std_logic;----时设置
      stop_sec,stop_min:out integer range 0 to 59;--显示时间分秒
      stop_hour:out integer range 0 to 23;----------显示时
      index:out std_logic;-----------标志定时结束
      disp:out std_logic);
end stop_watch;
architecture arch of stop_watch is
 signal a_sec,a_min:integer range 0 to 59;
 signal a_hour:integer range 0 to 23;
begin
process(stop,ok,hzl)
begin
if rst='1' then index<='0'; disp<='0';
  elsif rising_edge(hzl) then 
     if stop='1' and ok='0' then 
     if sec_tune='1' then 
         if a_sec=59 then a_sec<=0;
              else a_sec<=a_sec +1; 
         end if;
      end if;
      if min_tune='1' then 
          if a_min=59 then a_min<=0;
               else a_min<=a_min +1;
          end if;
       end if;   
      disp<='1';
 elsif stop='1' and ok='1' then
       if a_sec=0 then 
         if a_min=0 then 
           if a_hour=0 then index<='1';
      disp<='0';
                else a_hour<=a_hour-1;
      a_min<=59;
      a_sec<=59;
           end if;
            else a_min<=a_min-1;
      a_sec<=59;
          end if;
        else a_sec<=a_sec - 1;
      index<='0';
      disp<='1';
        end if;
  else disp<='0';
  end if;
 end if;
end process;
stop_sec<=a_sec;
stop_min<=a_min;
stop_hour<=a_hour;
end arch;           
-------------------------------------------
--ibcd二进制BCD组件
-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-----输入输出定义
entity i60bcd is
port(interg: in integer range 0 to 59;
     ten : out std_logic_vector(3 downto 0);---十位BCD
     one : out std_logic_vector(3 downto 0));--个位BCD
end i60bcd;
------结构体功能的实现部分
architecture arch of i60bcd is
begin 
 process(interg)
 begin
  case interg is-----------------------------个位转换为BCD的向量表
    when 0|10|20|30|40|50 =>one<="0000";
    when 1|11|21|31|41|51 =>one<="0001";
    when 2|12|22|32|42|52 =>one<="0010";
    when 3|13|23|33|43|53 =>one<="0011";
    when 4|14|24|34|44|54 =>one<="0100";
    when 5|15|25|35|45|55 =>one<="0101";
    when 6|16|26|36|46|56 =>one<="0110";
    when 7|17|27|37|47|57 =>one<="0111";
    when 8|18|28|38|48|58 =>one<="1000";
    when 9|19|29|39|49|59 =>one<="1001";
    when others =>one<="1110";
  end case;
  case interg is---------------------------十位转换为BCD的向量表
    when 0|1|2|3|4|5|6|7|8|9 => ten <="0000";
    when 10|11|12|13|14|15|16|17|18|19 =>ten<="0001";
    when 20|21|22|23|24|25|26|27|28|29 =>ten<="0010";
    when 30|31|32|33|34|35|36|37|38|39 =>ten<="0011";
    when 40|41|42|43|44|45|46|47|48|49 =>ten<="0100";
    when 50|51|52|53|54|55|56|57|58|59 =>ten<="0101";
    when others =>ten<="1110";
  end case;
end process;
end arch;   

-----------------------------------------
--i24bcd组件,把小时数转换成二进制BCD码
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
---------实体输入输出定义
entity i24bcd is
port(interg :in integer range 0 to 23;
    ten :out std_logic_vector(3 downto 0);---小时数的十位
    one :out std_logic_vector(3 downto 0));--小时数的个位
end entity;
---------结构体的功能实现
architecture arch of i24bcd is
begin
 process(interg)
 begin
  case interg is----------------小时数的个位转换向量表
    when 0|10|20 =>one<="0000";
    when 1|11|21 =>one<="0001";
    when 2|12|22 =>one<="0010";
    when 3|13|23 =>one<="0011";
    when 4|14 =>one<="0100";
    when 5|15 =>one<="0101";
    when 6|16 =>one<="0110";
    when 7|17 =>one<="0111";
    when 8|18 =>one<="1000";
    when 9|19 =>one<="1001";
    when others =>one<="1110";
   end case;
   case interg is---------------小时数的十位转换向量表
    when 0|1|2|3|4|5|6|7|8|9 =>ten<="0000";
    when 10|11|12|13|14|15|16|17|18|19 =>ten<="0001";
    when 20|21|22|23 =>ten<="0010";
    when others =>ten<="1110";
   end case;
  end process;
end arch;
---------------------------------------------------
--scan4组件,七段显示器扫描输出电路模块
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity scan4 is
port (rst,clk : in std_logic;
     a,b,c,d : in std_logic_vector(6 downto 0);----分与秒的七段LED显示器输入
     pa,pb,pc,pd : out std_logic;
     mux_out:out std_logic_vector(6 downto 0));----显示器的选择输出
end scan4;

architecture arch of scan4 is
 signal sel : std_logic_vector(1 downto 0);
begin
 process (rst,clk,a,b,c,d)
 begin
   if rst='1' then sel<="00";
   elsif rising_edge(clk) then
         sel<=sel + "01";-----利用视觉得停留进行循环显示,节省电
      case sel is
         when "00" => mux_out <= a;
                pa<= '1';pb<='0';pc<='0';pd<='0';
         when "01" => mux_out <= b;
                pa<= '0';pb<='1';pc<='0';pd<='0';
         when "10" => mux_out <= c;
                pa<= '0';pb<='0';pc<='1';pd<='0';
         when "11" => mux_out <=d;
                pa<='0'; pb<='0';pc<='0';pd<='1';
         when others => mux_out <="1011111";---显示错误E
       end case;
   end if;
 end process;
end arch;
--------------------------------------
--scan2组件,小时数的LED显示
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity scan2 is
port(rst,clk : in std_logic;
    a,b :in std_logic_vector(6 downto 0);---LED显示器输入
    pa,pb:out std_logic;
    mux_out: out std_logic_vector(6 downto 0));--轮流输出至多路输出
end scan2;

architecture arch of scan2 is
 signal sel : std_logic_vector (1 downto 0);
begin
process(rst,clk,a,b)
begin
 if rst='1' then sel<="00";
 elsif rising_edge(clk) then
      sel<= sel + "01";--利用人的视觉停留循环显示小时数,节电
    case sel is
      when "00" => mux_out <=a;
              pa<='1';pb<='0';
      when "01" => pa <='0';pb<='0';
      when "10" => mux_out <=b;
              pa<='0';pb<='1';
      when "11" => pa <='0';pb<= '0';
      when others => mux_out <= "1011111";--显示错误E
     end case;
  end if;
end process;
end arch;
----------------------------------------
--bin2led组件,把二进制BCD转换成十进制数显示
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-----实体输入输出定义
entity bin2led is
port (bin : in std_logic_vector (3 downto 0);---四位BCD二进制输入
     led : out std_logic_vector (6 downto 0));---七位LED显示
end bin2led;
-----结构体功能实现
architecture arch of bin2led is
begin
--segment encoding
--0
-- ---
-- 5 | | 1
-- --- <- 6
-- 4 | | 2
-- ---
--3
--anode_common 7_segment led
 with bin select
   led<="1111001" when "0001",--1
        "0100100" when "0010",--2
        "0110000" when "0011",--3
        "0011001" when "0100",--4
        "0010010" when "0101",--5
        "0000010" when "0110",--6
        "1111000" when "0111",--7
        "0000000" when "1000",--8
        "0010000" when "1001",--9
        "1000000" when "0000",--0
        "0000110" when others;--显示错误：E
end arch;