an_dcfifo_top.vo

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输

// synopsys translate_off
defparam \q[18]~output .bus_hold = "false";
defparam \q[18]~output .open_drain_output = "false";
defparam \q[18]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y17_N51
stratixiii_io_obuf \q[19]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [19]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[19]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[19]~output .bus_hold = "false";
defparam \q[19]~output .open_drain_output = "false";
defparam \q[19]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y22_N2
stratixiii_io_obuf \q[20]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [20]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[20]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[20]~output .bus_hold = "false";
defparam \q[20]~output .open_drain_output = "false";
defparam \q[20]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y22_N95
stratixiii_io_obuf \q[21]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [21]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[21]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[21]~output .bus_hold = "false";
defparam \q[21]~output .open_drain_output = "false";
defparam \q[21]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y17_N51
stratixiii_io_obuf \q[22]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [22]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[22]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[22]~output .bus_hold = "false";
defparam \q[22]~output .open_drain_output = "false";
defparam \q[22]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y22_N64
stratixiii_io_obuf \q[23]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [23]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[23]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[23]~output .bus_hold = "false";
defparam \q[23]~output .open_drain_output = "false";
defparam \q[23]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y21_N51
stratixiii_io_obuf \q[24]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [24]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[24]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[24]~output .bus_hold = "false";
defparam \q[24]~output .open_drain_output = "false";
defparam \q[24]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y17_N82
stratixiii_io_obuf \q[25]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [25]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[25]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[25]~output .bus_hold = "false";
defparam \q[25]~output .open_drain_output = "false";
defparam \q[25]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y22_N33
stratixiii_io_obuf \q[26]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [26]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[26]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[26]~output .bus_hold = "false";
defparam \q[26]~output .open_drain_output = "false";
defparam \q[26]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y22_N64
stratixiii_io_obuf \q[27]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [27]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[27]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[27]~output .bus_hold = "false";
defparam \q[27]~output .open_drain_output = "false";
defparam \q[27]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y19_N82
stratixiii_io_obuf \q[28]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [28]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[28]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[28]~output .bus_hold = "false";
defparam \q[28]~output .open_drain_output = "false";
defparam \q[28]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y19_N113
stratixiii_io_obuf \q[29]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [29]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[29]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[29]~output .bus_hold = "false";
defparam \q[29]~output .open_drain_output = "false";
defparam \q[29]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y21_N51
stratixiii_io_obuf \q[30]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [30]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[30]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[30]~output .bus_hold = "false";
defparam \q[30]~output .open_drain_output = "false";
defparam \q[30]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y16_N113
stratixiii_io_obuf \q[31]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [31]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[31]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[31]~output .bus_hold = "false";
defparam \q[31]~output .open_drain_output = "false";
defparam \q[31]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at CLKCTRL_G3
stratixiii_clkena \rvclk~inputclkctrl (
	.inclk(\rvclk~input_o ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\rvclk~inputclkctrl_outclk ),
	.enaout());
// synopsys translate_off
defparam \rvclk~inputclkctrl .clock_type = "global clock";
defparam \rvclk~inputclkctrl .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at MLABCELL_X1_Y20_N20
stratixiii_lcell_comb \rdctrl_logic|Add1~136 (
// Equation(s):
// \rdctrl_logic|Add1~136_sumout  = SUM(( \rdctrl_logic|word_count_o [0] ) + ( VCC ) + ( !VCC ))
// \rdctrl_logic|Add1~137  = CARRY(( \rdctrl_logic|word_count_o [0] ) + ( VCC ) + ( !VCC ))

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(!\rdctrl_logic|word_count_o [0]),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(),
	.sumout(\rdctrl_logic|Add1~136_sumout ),
	.cout(\rdctrl_logic|Add1~137 ),
	.shareout());
// synopsys translate_off
defparam \rdctrl_logic|Add1~136 .extended_lut = "off";
defparam \rdctrl_logic|Add1~136 .lut_mask = 64'h00000000000000FF;
defparam \rdctrl_logic|Add1~136 .shared_arith = "off";
// synopsys translate_on

// atom is at CLKCTRL_G1
stratixiii_clkena \reset~inputclkctrl (
	.inclk(\reset~input_o ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\reset~inputclkctrl_outclk ),
	.enaout());
// synopsys translate_off
defparam \reset~inputclkctrl .clock_type = "global clock";
defparam \reset~inputclkctrl .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at MLABCELL_X26_Y21_N16
stratixiii_lcell_comb \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~7 (
// Equation(s):
// \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~7_combout  = !\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(!\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q ),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~7_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~7 .extended_lut = "off";
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~7 .lut_mask = 64'hFF00FF00FF00FF00;
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~7 .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X26_Y21_N17