asyn_fifo.vo

FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输

// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 8.0 Build 215 05/29/2008 SJ Full Version"

// DATE "08/28/2008 17:14:40"

// 
// Device: Altera EP2C35F672C7 Package FBGA672
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ns/ 1 ps

module asyn_fifo (
	iCLK1,
	iRST,
	iCLK2,
	iDATA,
	iDVAL,
	oDVAL,
	oDATA);
input 	iCLK1;
input 	iRST;
input 	iCLK2;
input 	[7:0] iDATA;
input 	iDVAL;
output 	oDVAL;
output 	[7:0] oDATA;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("asyn_fifo_v.sdo");
// synopsys translate_on

wire \dut0|dcfifo_component|auto_generated|wrptr_gp|parity~combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|parity~combout ;
wire \dut0|dcfifo_component|auto_generated|p0addr~regout ;
wire \dut0|dcfifo_component|auto_generated|rdempty_eq_comp_aeb_int~87_combout ;
wire \dut1|state.WRITE~regout ;
wire \dut0|dcfifo_component|auto_generated|wrfull_eq_comp_aeb_int~84_combout ;
wire \dut1|always1~0_combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|parity_ff~regout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|parity_ff~regout ;
wire \iDVAL~combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[6]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[3]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[11]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[1]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[4]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[2]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[6]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[11]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[1]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[4]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|p0addr~feeder_combout ;
wire \iCLK2~combout ;
wire \iCLK2~clkctrl_outclk ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|parity~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera0~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera1~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera2~combout ;
wire \dut0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]~feeder_combout ;
wire \iRST~combout ;
wire \iRST~clkctrl_outclk ;
wire \dut0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]~clkctrl_outclk ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera2~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera3~combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera3~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera4~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera5~combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera5~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera6~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera7~combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera7~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera8~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera9~combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera9~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera10~combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera10~COUT ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera11~combout ;
wire \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[8]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[8]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera8~combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g[8]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rdempty_eq_comp_aeb_int~90_combout ;
wire \dut0|dcfifo_component|auto_generated|valid_rdreq~combout ;
wire \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[6]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera6~combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rdempty_eq_comp_aeb_int~84_combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera1~combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g[1]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera6~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera7~combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[7]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rdempty_eq_comp_aeb_int~86_combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera4~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera5~combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[5]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera8~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera9~combout ;
wire \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[9]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g[9]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rdempty_eq_comp_aeb_int~85_combout ;
wire \dut0|dcfifo_component|auto_generated|rdempty_eq_comp_aeb_int~88_combout ;
wire \dut0|dcfifo_component|auto_generated|rdcnt_addr_ena~2_combout ;
wire \dut0|dcfifo_component|auto_generated|rdcnt_addr_ena~combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera0~combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[0]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[0]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g[10]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[10]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|parity~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera0~combout ;
wire \dut0|dcfifo_component|auto_generated|wrfull_eq_comp_aeb_int~89_combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[2]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[2]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera1~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera2~combout ;
wire \dut0|dcfifo_component|auto_generated|wrfull_eq_comp_aeb_int~90_combout ;
wire \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera4~combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[4]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|wrfull_eq_comp_aeb_int~87_combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[5]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[5]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|wrfull_eq_comp_aeb_int~85_combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[1]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[1]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|wrfull_eq_comp_aeb_int~86_combout ;
wire \dut0|dcfifo_component|auto_generated|wrfull_eq_comp_aeb_int~88_combout ;
wire \dut0|dcfifo_component|auto_generated|valid_wrreq~combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera0~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera1~combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera2~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera3~combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera3~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera4~combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera5~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera6~combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera7~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera8~combout ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera9~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera10~combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[10]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[10]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[0]~feeder_combout ;
wire \dut0|dcfifo_component|auto_generated|rdempty_eq_comp_aeb_int~89_combout ;
wire \dut2|Selector0~6_combout ;
wire \dut2|state.READY~regout ;
wire \dut2|state.READ~regout ;
wire \iCLK1~combout ;
wire \iCLK1~clkctrl_outclk ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera10~COUT ;
wire \dut0|dcfifo_component|auto_generated|wrptr_gp|countera11~combout ;
wire [11:0] \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a ;
wire [11:0] \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a ;
wire [11:0] \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a ;
wire [11:0] \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a ;
wire [0:0] \dut0|dcfifo_component|auto_generated|rdaclr|dffe7a ;
wire [7:0] \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|q_a ;
wire [11:0] \dut0|dcfifo_component|auto_generated|wrptr_gp|counter_ffa ;
wire [11:0] \dut0|dcfifo_component|auto_generated|rdptr_g1p|counter_ffa ;
wire [11:0] \dut0|dcfifo_component|auto_generated|delayed_wrptr_g ;
wire [10:0] \dut0|dcfifo_component|auto_generated|ram_address_a ;
wire [10:0] \dut0|dcfifo_component|auto_generated|ram_address_b ;
wire [11:0] \dut0|dcfifo_component|auto_generated|rdptr_g ;
wire [7:0] \iDATA~combout ;

wire [1:0] \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a0_PORTADATAOUT_bus ;
wire [1:0] \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a2_PORTADATAOUT_bus ;
wire [1:0] \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a4_PORTADATAOUT_bus ;
wire [1:0] \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a6_PORTADATAOUT_bus ;

assign \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|q_a [0] = \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a0_PORTADATAOUT_bus [0];
assign \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|q_a [1] = \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a0_PORTADATAOUT_bus [1];

assign \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|q_a [2] = \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a2_PORTADATAOUT_bus [0];
assign \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|q_a [3] = \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a2_PORTADATAOUT_bus [1];

assign \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|q_a [4] = \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a4_PORTADATAOUT_bus [0];
assign \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|q_a [5] = \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a4_PORTADATAOUT_bus [1];

assign \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|q_a [6] = \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a6_PORTADATAOUT_bus [0];
assign \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|q_a [7] = \dut0|dcfifo_component|auto_generated|fifo_ram|altsyncram5|ram_block6a6_PORTADATAOUT_bus [1];

// atom is at LCCOMB_X30_Y23_N4
cycloneii_lcell_comb \dut0|dcfifo_component|auto_generated|wrptr_gp|parity (
// Equation(s):
// \dut0|dcfifo_component|auto_generated|wrptr_gp|parity~combout  = \dut0|dcfifo_component|auto_generated|wrptr_gp|parity_ff~regout  & (\dut0|dcfifo_component|auto_generated|valid_wrreq~combout  $ VCC) # 
// !\dut0|dcfifo_component|auto_generated|wrptr_gp|parity_ff~regout  & \dut0|dcfifo_component|auto_generated|valid_wrreq~combout  & VCC
// \dut0|dcfifo_component|auto_generated|wrptr_gp|parity~COUT  = CARRY(\dut0|dcfifo_component|auto_generated|wrptr_gp|parity_ff~regout  & \dut0|dcfifo_component|auto_generated|valid_wrreq~combout )

	.dataa(\dut0|dcfifo_component|auto_generated|wrptr_gp|parity_ff~regout ),
	.datab(\dut0|dcfifo_component|auto_generated|valid_wrreq~combout ),
	.datac(vcc),
	.datad(vcc),
	.cin(gnd),
	.combout(\dut0|dcfifo_component|auto_generated|wrptr_gp|parity~combout ),
	.cout(\dut0|dcfifo_component|auto_generated|wrptr_gp|parity~COUT ));
// synopsys translate_off
defparam \dut0|dcfifo_component|auto_generated|wrptr_gp|parity .lut_mask = 16'h6688;
defparam \dut0|dcfifo_component|auto_generated|wrptr_gp|parity .sum_lutc_input = "cin";
// synopsys translate_on

// atom is at LCCOMB_X28_Y22_N6
cycloneii_lcell_comb \dut0|dcfifo_component|auto_generated|rdptr_g1p|parity (
// Equation(s):
// \dut0|dcfifo_component|auto_generated|rdptr_g1p|parity~combout  = \dut0|dcfifo_component|auto_generated|rdptr_g1p|parity_ff~regout  & (\dut0|dcfifo_component|auto_generated|rdcnt_addr_ena~combout  $ VCC) # 
// !\dut0|dcfifo_component|auto_generated|rdptr_g1p|parity_ff~regout  & \dut0|dcfifo_component|auto_generated|rdcnt_addr_ena~combout  & VCC
// \dut0|dcfifo_component|auto_generated|rdptr_g1p|parity~COUT  = CARRY(\dut0|dcfifo_component|auto_generated|rdptr_g1p|parity_ff~regout  & \dut0|dcfifo_component|auto_generated|rdcnt_addr_ena~combout )

	.dataa(\dut0|dcfifo_component|auto_generated|rdptr_g1p|parity_ff~regout ),
	.datab(\dut0|dcfifo_component|auto_generated|rdcnt_addr_ena~combout ),
	.datac(vcc),
	.datad(vcc),
	.cin(gnd),
	.combout(\dut0|dcfifo_component|auto_generated|rdptr_g1p|parity~combout ),
	.cout(\dut0|dcfifo_component|auto_generated|rdptr_g1p|parity~COUT ));
// synopsys translate_off
defparam \dut0|dcfifo_component|auto_generated|rdptr_g1p|parity .lut_mask = 16'h6688;
defparam \dut0|dcfifo_component|auto_generated|rdptr_g1p|parity .sum_lutc_input = "cin";
// synopsys translate_on

// atom is at LCFF_X24_Y22_N25
cycloneii_lcell_ff \dut0|dcfifo_component|auto_generated|p0addr (
	.clk(\iCLK2~clkctrl_outclk ),
	.datain(\dut0|dcfifo_component|auto_generated|p0addr~feeder_combout ),
	.sdata(gnd),
	.aclr(!\dut0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]~clkctrl_outclk ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\dut0|dcfifo_component|auto_generated|p0addr~regout ));

// atom is at LCFF_X27_Y23_N21
cycloneii_lcell_ff \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[11] (