up3_clock.tan.summary

用vhdl设计实现的多功能电子钟

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.781 ns
From           : key_data
To             : ps2:U1|c_state.idle
From Clock     : --
To Clock       : clk_48Mhz
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 19.410 ns
From           : ps2:U1|hit_1
To             : HIT_LED
From Clock     : clk_48Mhz
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 8.994 ns
From           : reset
To             : RESET_LED
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.424 ns
From           : MOD_DRD
To             : MODIFY_DATE_STATE.modify_year0
From Clock     : --
To Clock       : clk_48Mhz
Failed Paths   : 0

Type           : Clock Setup: 'clk_48Mhz'
Slack          : N/A
Required Time  : None
Actual Time    : 69.77 MHz ( period = 14.332 ns )
From           : BCD_MON1[3]
To             : BCD_DAY0[3]
From Clock     : clk_48Mhz
To Clock       : clk_48Mhz
Failed Paths   : 0

Type           : Clock Hold: 'clk_48Mhz'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : ps2:U1|leds[0]
To             : KEY_BCD[3]
From Clock     : clk_48Mhz
To Clock       : clk_48Mhz
Failed Paths   : 40

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 40

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