stimulus.vhd

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----------------------------------------------------------------------------
--
--  File:   stimulus.vhd
--  Rev:    3.0.0
--
--  This is a functional simulation model for a stimulus generator.
--  This is not synthesizable.  This file is only for simulation.
--
--  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use STD.TEXTIO.ALL;


entity stimulus is
  port (
        AD              : inout std_logic_vector(63 downto 0);
        CBE             : inout std_logic_vector( 7 downto 0);
        PAR             : inout std_logic;
        PAR64           : inout std_logic;
        FRAME_N         : inout std_logic;
        REQ64_N         : inout std_logic;
        TRDY_N          : inout std_logic;
        IRDY_N          : inout std_logic;
        STOP_N          : inout std_logic;
        DEVSEL_N        : inout std_logic;
        ACK64_N         : inout std_logic;
        IDSEL           : out   std_logic;
        INTR_A          : in    std_logic;
        PERR_N          : in    std_logic;
        SERR_N          : in    std_logic;
        RST_N           : out   std_logic;
        CLK             : out   std_logic;
        SINGLE          : out   std_logic;
        PARK            : out   std_logic;
        PING_DONE       : in    std_logic;
        PING_REQUEST32  : out   std_logic;
        PING_REQUEST64  : out   std_logic
  );
end stimulus;


architecture behav_arch of stimulus is
  
  constant TCLKH        : time := 7 ns;
  constant TCLKL        : time := 8 ns;
  constant TDEL         : time := 5 ns;
  constant HI_Z         : std_logic_vector(31 downto 0) := (others => 'Z');

  signal pciclk         : std_logic;
  signal pciclk_en      : std_logic;
  signal operation      : string(1 to 12) := (others => ' ');
  signal status_code    : std_logic_vector( 3 downto 0);

  signal reg_ad         : std_logic_vector(63 downto 0);
  signal adh_oe         : std_logic := '0';
  signal adl_oe         : std_logic := '0';
  signal reg_cbe        : std_logic_vector( 7 downto 0);
  signal cbeh_oe        : std_logic := '0';
  signal cbel_oe        : std_logic := '0';
  signal reg_par        : std_logic := '1';
  signal par_oe         : std_logic := '0';
  signal reg_par64      : std_logic := '1';
  signal par64_oe       : std_logic := '0';
  signal reg_frame_n    : std_logic := '1';
  signal frame_oe       : std_logic := '0';
  signal reg_req64_n    : std_logic := '1';
  signal req64_oe       : std_logic := '0';
  signal reg_trdy_n     : std_logic := '1';
  signal trdy_oe        : std_logic := '0';
  signal reg_irdy_n     : std_logic := '1';
  signal irdy_oe        : std_logic := '0';
  signal reg_stop_n     : std_logic := '1';
  signal stop_oe        : std_logic := '0';
  signal reg_devsel_n   : std_logic := '1';
  signal devsel_oe      : std_logic := '0';
  signal reg_ack64_n    : std_logic := '1';
  signal ack64_oe       : std_logic := '0';

  signal reg_idsel      : std_logic := '0';
  signal reg_rst_n      : std_logic := '0';
  signal reg_single     : std_logic := '0';
  signal reg_park       : std_logic := '0';
  signal reg_req32      : std_logic := '0';
  signal reg_req64      : std_logic := '0';


  -- Procedure to print messages to stdout
  procedure print(s: in string) is
    variable l: line;
  begin
    write(l, s);
    writeline(output,l);
  end print;


begin


  --  Define port hookup

  AD(63 downto 32) <= reg_ad(63 downto 32) after TDEL when adh_oe='1'
                      else (others=>'Z') after TDEL;
  AD(31 downto  0) <= reg_ad(31 downto  0) after TDEL when adl_oe='1'
                      else (others=>'Z') after TDEL;
  CBE(7 downto  4) <= reg_cbe(7 downto  4) after TDEL when cbeh_oe='1'
                      else (others=>'Z') after TDEL;
  CBE(3 downto  0) <= reg_cbe(3 downto  0) after TDEL when cbel_oe='1'
                      else (others=>'Z') after TDEL;
  PAR      <= reg_par after TDEL when par_oe='1' else 'Z' after TDEL;
  PAR64    <= reg_par64 after TDEL when par64_oe='1' else 'Z' after TDEL;
  FRAME_N  <= reg_frame_n after TDEL when frame_oe='1' else 'Z' after TDEL;
  REQ64_N  <= reg_req64_n after TDEL when req64_oe='1' else 'Z' after TDEL;
  TRDY_N   <= reg_trdy_n after TDEL when trdy_oe='1' else 'Z' after TDEL;
  IRDY_N   <= reg_irdy_n after TDEL when irdy_oe='1' else 'Z' after TDEL;
  STOP_N   <= reg_stop_n after TDEL when stop_oe='1' else 'Z' after TDEL;
  DEVSEL_N <= reg_devsel_n after TDEL when devsel_oe='1' else 'Z' after TDEL;
  ACK64_N  <= reg_ack64_n after TDEL when ack64_oe='1' else 'Z' after TDEL;
  IDSEL    <= reg_idsel after TDEL;
  RST_N    <= reg_rst_n after TDEL;
  SINGLE   <= reg_single after TDEL;
  PARK     <= reg_park after TDEL;
  PING_REQUEST32 <= reg_req32 after TDEL;
  PING_REQUEST64 <= reg_req64 after TDEL;


  -- PCI Clock Generation

  process
  begin
    pciclk <= '0';
    wait for TCLKL;
    pciclk <= pciclk_en;
    wait for TCLKH;
  end process;

  CLK <= pciclk;


  -- PCI Parity Generation

  process(pciclk)
  begin
    if (pciclk'event and pciclk='1') then
      reg_par <= CBE(0) xor CBE(1) xor CBE(2) xor CBE(3) xor
                 AD( 0) xor AD( 1) xor AD( 2) xor AD( 3) xor
                 AD( 4) xor AD( 5) xor AD( 6) xor AD( 7) xor
                 AD( 8) xor AD( 9) xor AD(10) xor AD(11) xor
                 AD(12) xor AD(13) xor AD(14) xor AD(15) xor
                 AD(16) xor AD(17) xor AD(18) xor AD(19) xor
                 AD(20) xor AD(21) xor AD(22) xor AD(23) xor
                 AD(24) xor AD(25) xor AD(26) xor AD(27) xor
                 AD(28) xor AD(29) xor AD(30) xor AD(31)
                 after TDEL;
      par_oe <= adl_oe after TDEL;
    end if;
  end process;

  process(pciclk)
  begin
    if (pciclk'event and pciclk='1') then
      reg_par64 <= CBE(4) xor CBE(5) xor CBE(6) xor CBE(7) xor
                   AD(32) xor AD(33) xor AD(34) xor AD(35) xor
                   AD(36) xor AD(37) xor AD(38) xor AD(39) xor
                   AD(40) xor AD(41) xor AD(42) xor AD(43) xor
                   AD(44) xor AD(45) xor AD(46) xor AD(47) xor
                   AD(48) xor AD(49) xor AD(50) xor AD(51) xor
                   AD(52) xor AD(53) xor AD(54) xor AD(55) xor
                   AD(56) xor AD(57) xor AD(58) xor AD(59) xor
                   AD(60) xor AD(61) xor AD(62) xor AD(63)
                   after TDEL;
      par64_oe <= adh_oe after TDEL;
    end if;
  end process;


  -- This is the simulation process.  Begin
  -- by defining simulation procedures for
  -- the simulation script.

  process


  -- Task for waiting

  procedure INTERCYCLE_GAP is
  begin
    wait until pciclk'event and pciclk='1';
    wait until pciclk'event and pciclk='1';
    wait until pciclk'event and pciclk='1';
    wait until pciclk'event and pciclk='1';
  end INTERCYCLE_GAP;


  -- Task for monitoring the actual data transfer

  procedure XFER_STATUS
    (
    constant write_read : in bit_vector(3 downto 0);
    signal return_stat : out std_logic_vector(3 downto 0)
    ) is
    variable devsel_cnt : integer;
    variable trdy_cnt : integer;
  begin
    devsel_cnt := 0;
    trdy_cnt := 0;
    while ((To_X01(DEVSEL_N)='1') and (devsel_cnt<10)) loop
      wait until pciclk'event and pciclk='1';
      devsel_cnt := devsel_cnt + 1;
    end loop;
    while ((To_X01(TRDY_N)='1') and (To_X01(STOP_N)='1')
    and (trdy_cnt<16) and (devsel_cnt<10)) loop
      -- Turn off extension if not 64-bit
      if (write_read="1111") then
        adh_oe <= not ACK64_N;
      end if;
      cbeh_oe <= not ACK64_N;
      trdy_cnt := trdy_cnt + 1;
      wait until pciclk'event and pciclk='1';
    end loop;

    if (devsel_cnt<10) then
      if (trdy_cnt<=16) then
        if ( To_X01(TRDY_N)='0' and To_X01(STOP_N)='1' ) then
          if (write_read="1111") then
            print("  STM-->PNG: Normal Termination, Data Transferred");
          else
            print("  STM<--PNG: Normal Termination, Data Transferred");
          end if;
          return_stat <= "0001";
        elsif ( To_X01(TRDY_N)='0' and To_X01(STOP_N)='0' ) then
          if (write_read="1111") then
            print("  STM-->PNG: Disconnect, Data Transferred");
          else
            print("  STM<--PNG: Disconnect, Data Transferred");
          end if;
          return_stat <= "0010";
        elsif ( To_X01(TRDY_N)='1' and To_X01(STOP_N)='0'
                and To_X01(DEVSEL_N)='0' ) then
          if (write_read="1111") then
            print("  STM-->PNG: Retry, No Data Transferred");
          else
            print("  STM<--PNG: Retry, No Data Transferred");
          end if;
          return_stat <= "0011";
        elsif ( To_X01(TRDY_N)='1' and To_X01(STOP_N)='0'
                and To_X01(DEVSEL_N)='1' ) then
          if (write_read="1111") then
            print("  STM-->PNG: Target Abort, No Data Transferred");
          else
            print("  STM<--PNG: Target Abort, No Data Transferred");
          end if;
          return_stat <= "0100";
        elsif ( To_X01(TRDY_N)='1' and To_X01(STOP_N)='1' ) then
          print("  ERROR: Check Transfer Procedure");
          return_stat <= "0101";
        end if;
      else
        print("  ERROR: No Target Response");
        return_stat <= "0110";
      end if;
    else
      print("  ERROR: Master Abort");
      return_stat <= "0111";
    end if;
  end XFER_STATUS;


  -- Task for reading from the PCI64's configuration space
  -- Looks like 32-bit configurator plugged into 64-bit system
  -- or the PCI64 plugged into a 32-bit slot

  procedure READ_CONFIG
    (
    constant address : in bit_vector(31 downto 0)
    ) is 
  begin  
    print(" ");
    print("Reading Ping Config Reg...");
    operation <= "READ_CFG_32 ";
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '0';
      reg_irdy_n <= '1';
      reg_ad <= HI_Z & to_stdlogicvector(address);
      reg_cbe <= "ZZZZ" & "1010";
      reg_idsel <= '1';
      frame_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '1';
      cbel_oe <= '1';
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '1';
      reg_irdy_n <= '0';
      reg_cbe <= "ZZZZ" & "0000";
      reg_idsel <= '0';
      frame_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '0';
      cbel_oe <= '1';
      XFER_STATUS("0000", status_code);
      wait for 1 ns;
      reg_irdy_n <= '1';
      frame_oe <= '0';
      irdy_oe <= '1';
      adl_oe <= '0';
      cbel_oe <= '0';
    wait until pciclk'event and pciclk='1';
      frame_oe <= '0';
      irdy_oe <= '0';
    wait until pciclk'event and pciclk='1';
    INTERCYCLE_GAP;
  end READ_CONFIG;


  -- Task for writing to the PCI64's configuration space
  -- Looks like 32-bit configurator plugged into 64-bit system
  -- or the PCI64 plugged into a 32-bit slot

  procedure WRITE_CONFIG
    (   
    constant address : in bit_vector(31 downto 0);
    constant data : in bit_vector(63 downto 0)
    ) is 
  begin
    print(" ");  
    print("Writing Ping Config Reg...");
    operation <= "WRITE_CFG_32";
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '0';
      reg_irdy_n <= '1';
      reg_ad <= HI_Z & to_stdlogicvector(address);
      reg_cbe <= "ZZZZ" & "1011";
      reg_idsel <= '1';
      frame_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '1';
      cbel_oe <= '1';
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '1';
      reg_irdy_n <= '0';
      reg_ad <= HI_Z & to_stdlogicvector(data(31 downto 0));
      reg_cbe <= "ZZZZ" & "0000";
      reg_idsel <= '0';
      frame_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '1';
      cbel_oe <= '1';
      XFER_STATUS("1111", status_code);
      wait for 1 ns;
      reg_irdy_n <= '1';
      frame_oe <= '0';
      irdy_oe <= '1';
      adl_oe <= '0';
      cbel_oe <= '0';
    wait until pciclk'event and pciclk='1';
      frame_oe <= '0';
      irdy_oe <= '0';
    wait until pciclk'event and pciclk='1';
    INTERCYCLE_GAP;
  end WRITE_CONFIG;


  -- Task for reading from the PCI64
  -- Looks like 32-bit agent plugged into 64-bit system
  -- or the PCI64 plugged into a 32-bit slot
 
  procedure READ32
    (
    constant command : in bit_vector(3 downto 0);
    constant address : in bit_vector(31 downto 0)
    ) is
  begin
    print(" ");
    print("Reading Ping...");
    operation <= "READ_PNG_32 ";
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '0';
      reg_irdy_n <= '1';
      reg_ad <= HI_Z & to_stdlogicvector(address);
      reg_cbe <= "ZZZZ" & to_stdlogicvector(command);
      frame_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '1';
      cbel_oe <= '1';
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '1';
      reg_irdy_n <= '0';
      reg_cbe <= "ZZZZ" & "0000";
      frame_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '0';
      cbel_oe <= '1';
      XFER_STATUS("0000", status_code);
      wait for 1 ns;
      reg_irdy_n <= '1';
      frame_oe <= '0';
      irdy_oe <= '1';
      adl_oe <= '0';