stimulus.vhd

来自「xilinx官方PCIcore 有详细说明文档」· VHDL 代码 · 共 1,210 行 · 第 1/3 页

      cbel_oe <= '0';
    wait until pciclk'event and pciclk='1';
      frame_oe <= '0';
      irdy_oe <= '0';
    wait until pciclk'event and pciclk='1';
    INTERCYCLE_GAP;
  end READ32;


  -- Task for reading from the PCI64
  -- Looks like 64-bit agent plugged into 64-bit system
  -- attempting a 64-bit transfer
 
  procedure READ64
    (
    constant command : in bit_vector(3 downto 0);
    constant address : in bit_vector(31 downto 0)
    ) is 
  begin  
    print(" ");
    print("Reading Ping...");
    operation <= "READ_PNG_64 ";
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '0';
      reg_req64_n <= '0';
      reg_irdy_n <= '1';
      reg_ad <= to_stdlogicvector(X"00000000" & address);
      reg_cbe <= "0000" & to_stdlogicvector(command);
      frame_oe <= '1';
      req64_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '1';
      adh_oe <= '1';
      cbel_oe <= '1';
      cbeh_oe <= '1';
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '1';
      reg_req64_n <= '1';
      reg_irdy_n <= '0';
      reg_cbe <= "0000" & "0000";
      frame_oe <= '1';
      req64_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '0';
      adh_oe <= '0';
      cbel_oe <= '1';
      cbeh_oe <= '1';
      XFER_STATUS("0000", status_code);
      wait for 1 ns;
      reg_irdy_n <= '1';
      frame_oe <= '0';
      req64_oe <= '0';
      irdy_oe <= '1';
      adl_oe <= '0';
      adh_oe <= '0';
      cbel_oe <= '0';
      cbeh_oe <= '0';
    wait until pciclk'event and pciclk='1';
      frame_oe <= '0';
      req64_oe <= '0';
      irdy_oe <= '0';
    wait until pciclk'event and pciclk='1';
    INTERCYCLE_GAP;
  end READ64;


  -- Task for writing to the PCI64
  -- Looks like 32-bit agent plugged into 64-bit system
  -- or the PCI64 plugged into a 32-bit slot
 
  procedure WRITE32
    (    
    constant command : in bit_vector(3 downto 0);
    constant address : in bit_vector(31 downto 0);
    constant data : in bit_vector(63 downto 0)
    ) is 
  begin  
    print(" ");
    print("Writing Ping...");
    operation <= "WRITE_PNG_32";
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '0';
      reg_irdy_n <= '1';
      reg_ad <= HI_Z & to_stdlogicvector(address);
      reg_cbe <= "ZZZZ" & to_stdlogicvector(command);
      frame_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '1';
      cbel_oe <= '1';
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '1';
      reg_irdy_n <= '0';
      reg_ad <= HI_Z & to_stdlogicvector(data(31 downto 0));
      reg_cbe <= "ZZZZ" & "0000";
      frame_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '1';
      cbel_oe <= '1';
      XFER_STATUS("1111", status_code);
      wait for 1 ns;
      reg_irdy_n <= '1';
      frame_oe <= '0';
      irdy_oe <= '1';
      adl_oe <= '0';
      cbel_oe <= '0';
    wait until pciclk'event and pciclk='1';
      frame_oe <= '0';
      irdy_oe <= '0';
    wait until pciclk'event and pciclk='1';
    INTERCYCLE_GAP;
  end WRITE32;


  -- Task for writing to the PCI64
  -- Looks like 64-bit agent plugged into 64-bit system
  -- attempting a 64-bit transfer
 
  procedure WRITE64
    (    
    constant command : in bit_vector(3 downto 0);
    constant address : in bit_vector(31 downto 0);
    constant data : in bit_vector(63 downto 0)
    ) is
  begin 
    print(" ");
    print("Writing Ping...");
    operation <= "WRITE_PNG_64";
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '0';
      reg_req64_n <= '0';
      reg_irdy_n <= '1';
      reg_ad <= to_stdlogicvector(X"00000000" & address);
      reg_cbe <= "0000" & to_stdlogicvector(command);
      frame_oe <= '1';
      req64_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '1';
      adh_oe <= '1';
      cbel_oe <= '1';
      cbeh_oe <= '1';
    wait until pciclk'event and pciclk='1';
      reg_frame_n <= '1';
      reg_req64_n <= '1';
      reg_irdy_n <= '0';
      reg_ad <= to_stdlogicvector(data);
      reg_cbe <= "0000" & "0000";
      frame_oe <= '1';
      req64_oe <= '1';
      irdy_oe <= '1';
      adl_oe <= '1';
      adh_oe <= '1';
      cbel_oe <= '1';
      cbeh_oe <= '1';
      XFER_STATUS("1111", status_code);
      wait for 1 ns;
      reg_irdy_n <= '1';
      frame_oe <= '0';
      req64_oe <= '0';
      irdy_oe <= '1';
      adl_oe <= '0';
      adh_oe <= '0';
      cbel_oe <= '0';
      cbeh_oe <= '0';
    wait until pciclk'event and pciclk='1';
      frame_oe <= '0';
      req64_oe <= '0';
      irdy_oe <= '0';
    wait until pciclk'event and pciclk='1';
    INTERCYCLE_GAP;
  end WRITE64;


  -- Task for starting 32-bit transfer

  procedure MOVE32 is
  begin
    wait until pciclk'event and pciclk='1';
    reg_req32 <= '1';
    wait until pciclk'event and pciclk='1';
    reg_req32 <= '0';
    wait until pciclk'event and pciclk='1' and PING_DONE='1';
  end MOVE32;


  -- Task for starting 64-bit transfer

  procedure MOVE64 is
  begin
    wait until pciclk'event and pciclk='1';
    reg_req64 <= '1';
    wait until pciclk'event and pciclk='1';
    reg_req64 <= '0';
    wait until pciclk'event and pciclk='1' and PING_DONE='1';
  end MOVE64;


  -- Tasks for bus parking

  procedure ARB_PARK is
  begin
    wait until pciclk'event and pciclk='1';
    reg_park <= '1';
    wait until pciclk'event and pciclk='1';
  end ARB_PARK;

  procedure ARB_FREE is
  begin
    wait until pciclk'event and pciclk='1';
    reg_park <= '0';
    wait until pciclk'event and pciclk='1';
  end ARB_FREE;


  -- Tasks for single cycle grants
 
  procedure ARB_SINGLE is
  begin  
    wait until pciclk'event and pciclk='1';
    reg_single <= '1';
    wait until pciclk'event and pciclk='1';
  end ARB_SINGLE;
 
  procedure ARB_FOLLOW is
  begin  
    wait until pciclk'event and pciclk='1';
    reg_single <= '0';
    wait until pciclk'event and pciclk='1';
  end ARB_FOLLOW;  


  -- Begin the actual simulation script

  begin
    -- start by setting up all signals
    operation <= "SYSTEM RESET";
    pciclk_en <= '1';
    reg_ad <= (others => '0');
    adh_oe <= '0';
    adl_oe <= '0';
    reg_cbe <= (others => '0');
    cbeh_oe <= '0';
    cbel_oe <= '0';
    reg_frame_n <= '1';
    frame_oe <= '0';
    reg_req64_n <= '1';
    req64_oe <= '0';
    reg_trdy_n <= '1';
    trdy_oe <= '0';
    reg_irdy_n <= '1';
    irdy_oe <= '0';
    reg_stop_n <= '1';
    stop_oe <= '0';
    reg_devsel_n <= '1';
    devsel_oe <= '0';
    reg_ack64_n <= '1';
    ack64_oe <= '0';
    reg_idsel <= '0';
    reg_rst_n <= '0';
    reg_single <= '0';
    reg_park <= '0';
    reg_req32 <= '0';
    reg_req64 <= '0';

    -- release system reset
    INTERCYCLE_GAP;
    reg_rst_n <= '1';
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    print(" ");
    print("System Reset Complete...");
    print(" ");
 
 
    -- read device and vendor id
    READ_CONFIG(X"00000000");

    -- write latency timer
    WRITE_CONFIG(X"0000000c", X"000000000000ff00");
    READ_CONFIG(X"0000000c");


    -- setup io base address register
    WRITE_CONFIG(X"00000010", X"0000000010000000");
    READ_CONFIG(X"00000010");

    -- setup mem32 base address register
    WRITE_CONFIG(X"00000014", X"0000000020000000");
    READ_CONFIG(X"00000014");

    -- setup mem64 base address register
    WRITE_CONFIG(X"00000018", X"0000000030000000");
    READ_CONFIG(X"00000018");

    -- setup command register to enable mastering
    WRITE_CONFIG(X"00000004", X"00000000ff000147"); 
    READ_CONFIG(X"00000004");


    -- read io space
    READ32("0010", X"10000000");
 
    -- read io space
    READ64("0010", X"10000000");
 
 
    -- write io space
    WRITE32("0011", X"10000000", X"0000000020202020");
    READ32("0010", X"10000000");
 
    -- write io space
    WRITE64("0011", X"10000000", X"0000000030303030");
    READ64("0010", X"10000000");
 

    -- read mem32 space
    READ32("0110", X"20000000");
 
    -- read mem32 space
    READ64("0110", X"20000000");


    -- write mem32 space
    WRITE32("0111", X"20000000", X"0000000016161616");
    READ32("0110", X"20000000");

    -- write mem32 space
    WRITE64("0111", X"20000000", X"0000000008080808");
    READ64("0110", X"20000000");


    -- read mem64 space
    READ32("0110", X"30000000");
 
    -- read mem64 space
    READ64("0110", X"30000000");


    -- write mem64 space
    WRITE32("0111", X"30000000", X"a5a5a5a5a5a5a5a5");
    READ32("0110", X"30000000");

    -- write mem64 space
    WRITE64("0111", X"30000000", X"5a5a5a5a5a5a5a5a");
    READ64("0110", X"30000000");


    print(" ");
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    print(" ");
    print("Performing 32-bit initiator transfers...");
    print(" ");


    -- set up one-dataphase 32-bit initiator  read to 32-bit target
    WRITE32("0011", X"10000000", X"0000000000000061");
    WRITE32("0111", X"20000000", X"0000000040000004");
    MOVE32;

    -- set up two-dataphase 32-bit initiator  read to 32-bit target
    WRITE32("0011", X"10000000", X"0000000000000062");
    WRITE32("0111", X"20000000", X"0000000040000008");
    MOVE32;

    -- set up three-dataphase 32-bit initiator  read to 32-bit target
    WRITE32("0011", X"10000000", X"0000000000000063");
    WRITE32("0111", X"20000000", X"0000000040000010");
    MOVE32;

    -- set up four-dataphase 32-bit initiator  read to 32-bit target
    WRITE32("0011", X"10000000", X"0000000000000064");
    WRITE32("0111", X"20000000", X"000000004000001c");
    MOVE32;

    -- set up one-dataphase 32-bit initiator write to 32-bit target
    WRITE32("0011", X"10000000", X"0000000080000061");
    WRITE32("0111", X"20000000", X"0000000040000004");
    MOVE32;

    -- set up two-dataphase 32-bit initiator write to 32-bit target
    WRITE32("0011", X"10000000", X"0000000080000062");
    WRITE32("0111", X"20000000", X"0000000040000008");
    MOVE32;

    -- set up three-dataphase 32-bit initiator write to 32-bit target
    WRITE32("0011", X"10000000", X"0000000080000063");
    WRITE32("0111", X"20000000", X"0000000040000010");
    MOVE32;

    -- set up four-dataphase 32-bit initiator write to 32-bit target
    WRITE32("0011", X"10000000", X"0000000080000064");
    WRITE32("0111", X"20000000", X"000000004000001c");
    MOVE32;