_primary.vhd

来自「软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity paobiao is
    port(
        CLK             : in     vl_logic;
        CLR             : in     vl_logic;
        PAUSE           : in     vl_logic;
        MSH             : out    vl_logic_vector(3 downto 0);
        MSL             : out    vl_logic_vector(3 downto 0);
        SH              : out    vl_logic_vector(3 downto 0);
        SL              : out    vl_logic_vector(3 downto 0);
        MH              : out    vl_logic_vector(3 downto 0);
        ML              : out    vl_logic_vector(3 downto 0)
    );
end paobiao;