_primary.vhd

来自「软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity paobiao_tb is
    generic(
        PERIOD          : integer := 20;
        DUTY_CYCLE      : real    := 0.500000;
        OFFSET          : integer := 0
    );
end paobiao_tb;