config_dac.hif

Verilog实现 spi接口的FPGA实现 通过仿真

Version 7.1 Build 156 04/30/2007 SJ Full Version
11
2401
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
config_dac
# storage
db|config_dac.(0).cnf
db|config_dac.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
config_dac.v
f45379f52024d83dc47df115a3f5a482
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
IDLE
00001
PARAMETER_UNSIGNED_BIN
DEF
START
00010
PARAMETER_UNSIGNED_BIN
DEF
INSTRUCTION
00100
PARAMETER_UNSIGNED_BIN
DEF
DATA
01000
PARAMETER_UNSIGNED_BIN
DEF
STOP
10000
PARAMETER_UNSIGNED_BIN
DEF
}
# hierarchies {
|
}
# lmf
e:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete