prev_cmp_config_dac.qmsg

Verilog实现 spi接口的FPGA实现 通过仿真

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Elaboration Quartus II " "Info: Running Quartus II Analysis & Elaboration" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 19 14:18:37 2008 " "Info: Processing started: Tue Aug 19 14:18:37 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off config_dac -c config_dac --analysis_and_elaboration " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off config_dac -c config_dac --analysis_and_elaboration" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "config_dac.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file config_dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 config_dac " "Info: Found entity 1: config_dac" {  } { { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "lsb_fist ad9777_spi_interface.v(43) " "Warning (10236): Verilog HDL Implicit Net warning at ad9777_spi_interface.v(43): created implicit net for \"lsb_fist\"" {  } { { "ad9777_spi_interface.v" "" { Text "D:/altera/71/config_dac/ad9777_spi_interface.v" 43 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ad9777_spi_interface.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ad9777_spi_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 ad9777_spi_interface " "Info: Found entity 1: ad9777_spi_interface" {  } { { "ad9777_spi_interface.v" "" { Text "D:/altera/71/config_dac/ad9777_spi_interface.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test_config_dac.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file test_config_dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 test_config_dac " "Info: Found entity 1: test_config_dac" {  } { { "test_config_dac.v" "" { Text "D:/altera/71/config_dac/test_config_dac.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "config_dac " "Info: Elaborating entity \"config_dac\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 config_dac.v(122) " "Warning (10230): Verilog HDL assignment warning at config_dac.v(122): truncated value with size 32 to match size of target (2)" {  } { { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Elaboration 0 s 1  Quartus II " "Info: Quartus II Analysis & Elaboration was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "131 " "Info: Allocated 131 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 19 14:18:38 2008 " "Info: Processing ended: Tue Aug 19 14:18:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}