test_config_dac.v

Verilog实现 spi接口的FPGA实现 通过仿真

`timescale 1ns/1ps
module test_config_dac();
reg       clk;
reg       resetb;
reg [4:0] wr_rd_addr;
reg       wr_en;
reg [7:0] wr_data;
reg       rd_en;

wire [7:0] rd_data;
wire       busy;
wire       rd_data_valid;
wire       spi_ncs,spi_sdio,spi_sdo,spi_sck;

initial 
begin
  clk=0;
  resetb=1;
  wr_rd_addr=1;
  wr_en=0;
  rd_en=0;
  wr_data=0;
#1000  wr_en=1;
       wr_data=8'h45;
#100 wr_en=0;
#30000 rd_en=1;
#100  rd_en=0;
#10000     $stop;
end

always  #25 clk=~clk;

config_dac config_dac(
   .clk(clk),
   .resetb(resetb),
   
   .wr_rd_addr(wr_rd_addr),
   .wr_en(wr_en),
   .wr_data(wr_data),
   .rd_en(rd_en),
   .rd_data(rd_data),
   .rd_data_valid(rd_data_valid),
   .busy(busy),

   .spi_ncs(spi_ncs),
   .spi_sdio(spi_sdio),
   .spi_sdo(spi_sdo),
   .spi_sck(spi_sck)
);

ad9777_spi_interface as9777_aspi_interface(
   .spi_ncs(spi_ncs),
   .spi_sck(spi_sck),
   .spi_sdio(spi_sdio),
   .spi_sdo(spi_sdo)
   
);

endmodule