ad9777_spi_interface.v.bak

Verilog实现 spi接口的FPGA实现 通过仿真

module ad9777_spi_interface(
   spi_ncs,
   spi_sck,
   spi_sdio,
   spi_sdo
);

input  spi_ncs;
input  spi_sck;
input  spi_sdio;
output spi_sdo;

wire   spi_ncs;
wire   spi_sck;
wire   spi_sdio;
reg    spi_sdo;

reg  [7:0] register[0:13];
wire       lsb_first;
reg        instruction;
reg  [7:0] data_temp;
reg  [4:0] addr;
integer    i;

initial 
begin
  register[0]=8'b0000_0000;
  register[1]=8'b0000_0100;
  register[2]=8'b0010_0000;
  register[3]=8'b0000_0000;
  register[4]=8'b0000_0000;
  register[5]=8'b0000_0000;
  register[6]=8'b0000_0000;
  register[7]=8'b0000_0000;
  register[8]=8'b0000_0000;
  register[9]=8'b0000_0000;
  register[10]=8'b0000_0000;
  register[11]=8'b0000_0000;
  register[12]=8'b0000_0000;
  register[13]=8'b0000_0000;
end

assign lsb_fist=0;//register[0][6];

always @(negedge spi_ncs)
begin
   Receive_Instruction;
   if(instruction==0)
     Receive_Data;
   else
     Send_Data;
end

task Receive_Instruction;
begin
  repeat(8)
  begin
    @(posedge spi_sck)
    if(lsb_first==0)
       data_temp={data_temp[6:0],spi_sdio};
    else
       data_temp={spi_sdio,data_temp[7:1]};
  end
  instruction=data_temp[7];
  addr=data_temp[4:0];
end
endtask

task Receive_Data;
begin
  repeat(8)
  begin
    @(posedge spi_sck)
    if(lsb_first==0)
       data_temp={data_temp[6:0],spi_sdio};
    else
       data_temp={spi_sdio,data_temp[7:1]};
  end
  register[addr]=data_temp;
end
endtask

task Send_Data;
begin
   for(i=0;i<8;i=i+1)
   begin
     @(negedge spi_sck)
     if(lsb_first==0)
       spi_sdo=register[addr][7-i];
     else
       spi_sdo=register[addr][i];
   end
end
endtask

endmodule