config_dac.map.rpt

Verilog实现 spi接口的FPGA实现 通过仿真

Analysis & Elaboration report for config_dac
Tue Aug 19 14:24:23 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Legal Notice
  3. Flow Summary
  4. Flow Settings
  5. Flow Non-Default Global Settings
  6. Flow Elapsed Time
  7. Flow Log
  8. Analysis & Elaboration Summary
  9. Analysis & Elaboration Settings
 10. Parameter Settings for User Entity Instance: Top-level Entity: |config_dac
 11. Analysis & Elaboration Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Flow Summary                                                                  ;
+------------------------------------+------------------------------------------+
; Flow Status                        ; Successful - Tue Aug 19 14:24:23 2008    ;
; Quartus II Version                 ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name                      ; config_dac                               ;
; Top-level Entity Name              ; config_dac                               ;
; Family                             ; Cyclone II                               ;
; Met timing requirements            ; N/A                                      ;
; Total logic elements               ; N/A until Partition Merge                ;
;     Total combinational functions  ; N/A until Partition Merge                ;
;     Dedicated logic registers      ; N/A until Partition Merge                ;
; Total registers                    ; N/A until Partition Merge                ;
; Total pins                         ; N/A until Partition Merge                ;
; Total virtual pins                 ; N/A until Partition Merge                ;
; Total memory bits                  ; N/A until Partition Merge                ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                ;
; Total PLLs                         ; N/A until Partition Merge                ;
+------------------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 08/19/2008 14:24:23 ;
; Main task         ; Compilation         ;
; Revision Name     ; config_dac          ;
+-------------------+---------------------+


+---------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                  ;
+------------------------+---------------------------+---------------+-------------+----------------+
; Assignment Name        ; Value                     ; Default Value ; Entity Name ; Section Id     ;
+------------------------+---------------------------+---------------+-------------+----------------+
; EDA_OUTPUT_DATA_FORMAT ; Verilog                   ; --            ; --          ; eda_simulation ;
; EDA_SIMULATION_TOOL    ; ModelSim-Altera (Verilog) ; <None>        ; --          ; --             ;
; EDA_TIME_SCALE         ; 1 ps                      ; --            ; --          ; eda_simulation ;
; PARTITION_NETLIST_TYPE ; SOURCE                    ; --            ; --          ; Top            ;
+------------------------+---------------------------+---------------+-------------+----------------+


+---------------------------------------+
; Flow Elapsed Time                     ;
+------------------------+--------------+
; Module Name            ; Elapsed Time ;
+------------------------+--------------+
; Analysis & Elaboration ; 00:00:00     ;
; Total                  ; 00:00:00     ;
+------------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off config_dac -c config_dac --analysis_and_elaboration



+-------------------------------------------------------------------------------+