_primary.vhd

来自「verilog中调用门级电路的实验程序」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity flop_vlg_sample_tst is
    port(
        s1              : in     vl_logic;
        s2              : in     vl_logic;
        s3              : in     vl_logic;
        sampler_tx      : out    vl_logic
    );
end flop_vlg_sample_tst;