_primary.vhd

来自「verilog中调用门级电路的实验程序」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity flop_vlg_check_tst is
    port(
        o1              : in     vl_logic;
        o2              : in     vl_logic;
        sampler_rx      : in     vl_logic
    );
end flop_vlg_check_tst;