_deps

verilog中调用门级电路的实验程序

H 2141964 10 1 0 1 1 0 0 0 0
L 4 work 4 work
D 24 work.flop_vlg_sample_tst eAnBeUG<:lS]I1_3dGGRa0 0 0
2 4 fast 0 =;37I:YBhQke[5S_ESn=12 0 0 1