_primary.vhd

电机控制的程序例程

library verilog;
use verilog.vl_types.all;
entity bldc_ip is
    port(
        dbg_cs1         : out    vl_logic;
        dbg_cs0         : out    vl_logic;
        PHASEA_H        : out    vl_logic;
        PHASEA_L        : out    vl_logic;
        PHASEB_H        : out    vl_logic;
        PHASEB_L        : out    vl_logic;
        PHASEC_H        : out    vl_logic;
        PHASEC_L        : out    vl_logic;
        clk_76hz        : out    vl_logic;
        bdbl_start_motor: out    vl_logic;
        rpm_value       : out    vl_logic_vector(7 downto 0);
        HALL_A          : in     vl_logic;
        HALL_B          : in     vl_logic;
        HALL_C          : in     vl_logic;
        run             : in     vl_logic;
        stop            : in     vl_logic;
        plus            : in     vl_logic;
        minus           : in     vl_logic;
        cw_or_ccw       : in     vl_logic;
        pwm_freq_sel    : in     vl_logic;
        mst_or_bd_bl    : in     vl_logic;
        mstp_or_bl_md   : in     vl_logic;
        sys_clk         : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        rst_l           : in     vl_logic
    );
end bldc_ip;