_primary.vhd

来自「电机控制的程序例程」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity mux is
    port(
        y               : out    vl_logic;
        a               : in     vl_logic;
        b               : in     vl_logic;
        c               : in     vl_logic;
        d               : in     vl_logic;
        s               : in     vl_logic_vector(1 downto 0);
        clk             : in     vl_logic
    );
end mux;