_primary.vhd

来自「电机控制的程序例程」· VHDL 代码 · 共 34 行

library verilog;
use verilog.vl_types.all;
entity top_bldc is
    port(
        dbg_cs1         : out    vl_logic;
        dbg_cs0         : out    vl_logic;
        a_high          : out    vl_logic;
        a_low           : out    vl_logic;
        b_high          : out    vl_logic;
        b_low           : out    vl_logic;
        c_high          : out    vl_logic;
        c_low           : out    vl_logic;
        dutycycle_display: out    vl_logic_vector(7 downto 0);
        start_motor     : out    vl_logic;
        stop_motor      : out    vl_logic;
        bd_or_bl        : in     vl_logic;
        clk_76hz        : in     vl_logic;
        pwm_gen_clk2    : in     vl_logic;
        pwm_gen_clk1    : in     vl_logic;
        digital_rpm_plus: in     vl_logic;
        digital_rpm_minus: in     vl_logic;
        pwm_freq_sel    : in     vl_logic;
        bdbl_cw_or_ccw  : in     vl_logic;
        bl_mode         : in     vl_logic;
        start           : in     vl_logic;
        stop            : in     vl_logic;
        HALL_A          : in     vl_logic;
        HALL_B          : in     vl_logic;
        HALL_C          : in     vl_logic;
        sys_clk         : in     vl_logic;
        rst_l           : in     vl_logic
    );
end top_bldc;