_primary.vhd

来自「电机控制的程序例程」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity pwm_gen_bdbl is
    port(
        pwm_out         : out    vl_logic;
        pwm_on_or_off   : in     vl_logic;
        pwm_freq_sel    : in     vl_logic;
        pwm_gen_clk1    : in     vl_logic;
        pwm_gen_clk2    : in     vl_logic;
        dutycycle       : in     vl_logic_vector(7 downto 0);
        sys_clk         : in     vl_logic;
        rst_l           : in     vl_logic
    );
end pwm_gen_bdbl;