_primary.vhd

电机控制的程序例程

library verilog;
use verilog.vl_types.all;
entity recv_control is
    port(
        data_recv       : out    vl_logic;
        set_ri          : out    vl_logic;
        r_edge_baud_clk : out    vl_logic;
        rx_data         : out    vl_logic_vector(7 downto 0);
        RXD             : in     vl_logic;
        baud_clk        : in     vl_logic;
        sys_clk         : in     vl_logic;
        rst_l           : in     vl_logic
    );
end recv_control;