_primary.vhd

电机控制的程序例程

library verilog;
use verilog.vl_types.all;
entity bdbl_driver is
    port(
        dbg_cs1         : out    vl_logic;
        dbg_cs0         : out    vl_logic;
        phase           : out    vl_logic_vector(5 downto 0);
        start_motor     : out    vl_logic;
        stop_motor      : out    vl_logic;
        rst_stop        : out    vl_logic;
        stop_complete   : in     vl_logic;
        pwm             : in     vl_logic;
        stop            : in     vl_logic;
        bd_or_bl        : in     vl_logic;
        clk_prepos_time : in     vl_logic;
        bl_mode         : in     vl_logic;
        start           : in     vl_logic;
        bdbl_cw_or_ccw  : in     vl_logic;
        HALL_A          : in     vl_logic;
        HALL_B          : in     vl_logic;
        HALL_C          : in     vl_logic;
        sys_clk         : in     vl_logic;
        rst_l           : in     vl_logic
    );
end bdbl_driver;