_primary.vhd

电机控制的程序例程

library verilog;
use verilog.vl_types.all;
entity bd_bl_speedcontrol is
    port(
        dutycycle_display: out    vl_logic_vector(7 downto 0);
        dutycycle_pwm0  : out    vl_logic_vector(7 downto 0);
        stop_complete   : out    vl_logic;
        digital_rpm_minus: in     vl_logic;
        digital_rpm_plus: in     vl_logic;
        stop_motor      : in     vl_logic;
        start_motor     : in     vl_logic;
        clk_rampdown    : in     vl_logic;
        sys_clk         : in     vl_logic;
        rst_l           : in     vl_logic
    );
end bd_bl_speedcontrol;