clock.syr

dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过.

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : clock.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : clock
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : clock
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : clock.prj
Compiling included source file 'clock.v'
Module <clock> compiled.
Continuing compilation of source file 'clock.prj'
Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'clock.prj'
No errors in compilation
Analysis of file <clock.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <clock>.
WARNING:Xst:854 - "clock.v", line 12: Ignored initial statement.
WARNING:Xst:905 - "clock.v", line 30: The signals <sec> are missing in the sensitivity list of always block.
WARNING:Xst:905 - "clock.v", line 36: The signals <min> are missing in the sensitivity list of always block.
WARNING:Xst:905 - "clock.v", line 46: The signals <count, sec> are missing in the sensitivity list of always block.
Module <clock> is correct for synthesis.

Synthesizing Unit <clock>.
    Related source file is clock.v.
WARNING:Xst:737 - Found 1-bit latch for signal <keyen_reg>.
    Found 16x8-bit ROM for internal node.
    Found 4-bit adder for signal <$n0000> created at line 85.
    Found 4-bit adder for signal <$n0001> created at line 89.
    Found 4-bit adder for signal <$n0002> created at line 93.
    Found 4-bit adder for signal <$n0003> created at line 97.
    Found 23-bit adder for signal <$old_count_1>.
    Found 23-bit register for signal <count>.
    Found 4-bit 4-to-1 multiplexer for signal <ledbuf>.
    Found 16-bit register for signal <min>.
    Found 1-bit register for signal <sec>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred  40 D-type flip-flop(s).
	inferred   1 Latch(s).
	inferred   5 Adder/Subtracter(s).
	inferred  12 Multiplexer(s).
Unit <clock> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Registers                        : 18
  23-bit register                  : 1
  1-bit register                   : 17
# Latches                          : 1
  1-bit latch                      : 1
# Multiplexers                     : 2
  4-bit 4-to-1 multiplexer         : 1
  2-to-1 multiplexer               : 1
# Adders/Subtractors               : 5
  4-bit adder                      : 4
  23-bit adder                     : 1

=========================================================================


Starting low level synthesis...

Optimizing unit <clock> ...
=========================================================================
Final Results
Output File Name                   : clock
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Xors                             : 34
  1-bit xor2                       : 34

Design Statistics
# Edif Instances                   : 362
# I/Os                             : 15

=========================================================================
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