📄 dljpym.tan.rpt
字号:
; N/A ; None ; -6.621 ns ; key_in[6] ; F[2] ; clk ;
; N/A ; None ; -6.625 ns ; key_in[6] ; F[3] ; clk ;
; N/A ; None ; -6.824 ns ; key_in[11] ; F[3] ; clk ;
; N/A ; None ; -6.825 ns ; key_in[11] ; F[2] ; clk ;
; N/A ; None ; -6.859 ns ; key_in[2] ; N[1] ; clk ;
; N/A ; None ; -6.872 ns ; key_in[6] ; N[1] ; clk ;
; N/A ; None ; -6.915 ns ; key_in[10] ; N[2] ; clk ;
; N/A ; None ; -6.916 ns ; key_in[1] ; N[0] ; clk ;
; N/A ; None ; -6.933 ns ; key_in[8] ; N[0] ; clk ;
; N/A ; None ; -6.950 ns ; key_in[11] ; N[2] ; clk ;
; N/A ; None ; -6.972 ns ; key_in[2] ; F[2] ; clk ;
; N/A ; None ; -6.976 ns ; key_in[2] ; F[3] ; clk ;
; N/A ; None ; -6.995 ns ; key_in[3] ; N[0] ; clk ;
; N/A ; None ; -7.077 ns ; key_in[13] ; N[3] ; clk ;
; N/A ; None ; -7.099 ns ; key_in[2] ; N[2] ; clk ;
; N/A ; None ; -7.105 ns ; key_in[13] ; N[2] ; clk ;
; N/A ; None ; -7.120 ns ; key_in[7] ; F[2] ; clk ;
; N/A ; None ; -7.124 ns ; key_in[7] ; F[3] ; clk ;
; N/A ; None ; -7.146 ns ; key_in[8] ; F[3] ; clk ;
; N/A ; None ; -7.147 ns ; key_in[8] ; F[2] ; clk ;
; N/A ; None ; -7.152 ns ; key_in[13] ; N[0] ; clk ;
; N/A ; None ; -7.161 ns ; key_in[10] ; N[1] ; clk ;
; N/A ; None ; -7.185 ns ; key_in[4] ; N[1] ; clk ;
; N/A ; None ; -7.196 ns ; key_in[11] ; N[1] ; clk ;
; N/A ; None ; -7.222 ns ; key_in[6] ; N[2] ; clk ;
; N/A ; None ; -7.265 ns ; key_in[1] ; N[2] ; clk ;
; N/A ; None ; -7.271 ns ; key_in[7] ; N[3] ; clk ;
; N/A ; None ; -7.279 ns ; key_in[6] ; F[0] ; clk ;
; N/A ; None ; -7.282 ns ; key_in[8] ; N[2] ; clk ;
; N/A ; None ; -7.313 ns ; key_in[3] ; N[2] ; clk ;
; N/A ; None ; -7.321 ns ; key_in[9] ; N[0] ; clk ;
; N/A ; None ; -7.346 ns ; key_in[7] ; N[0] ; clk ;
; N/A ; None ; -7.390 ns ; key_in[2] ; N[0] ; clk ;
; N/A ; None ; -7.447 ns ; key_in[7] ; N[1] ; clk ;
; N/A ; None ; -7.452 ns ; key_in[12] ; N[3] ; clk ;
; N/A ; None ; -7.511 ns ; key_in[1] ; N[1] ; clk ;
; N/A ; None ; -7.513 ns ; key_in[6] ; N[0] ; clk ;
; N/A ; None ; -7.515 ns ; key_in[7] ; N[2] ; clk ;
; N/A ; None ; -7.527 ns ; key_in[12] ; N[0] ; clk ;
; N/A ; None ; -7.528 ns ; key_in[8] ; N[1] ; clk ;
; N/A ; None ; -7.539 ns ; key_in[9] ; F[3] ; clk ;
; N/A ; None ; -7.540 ns ; key_in[9] ; F[2] ; clk ;
; N/A ; None ; -7.554 ns ; key_in[4] ; N[2] ; clk ;
; N/A ; None ; -7.570 ns ; key_in[3] ; N[3] ; clk ;
; N/A ; None ; -7.640 ns ; key_in[2] ; F[0] ; clk ;
; N/A ; None ; -7.670 ns ; key_in[9] ; N[2] ; clk ;
; N/A ; None ; -7.745 ns ; key_in[12] ; N[1] ; clk ;
; N/A ; None ; -7.747 ns ; key_in[13] ; N[1] ; clk ;
; N/A ; None ; -7.813 ns ; key_in[12] ; N[2] ; clk ;
; N/A ; None ; -7.845 ns ; key_in[4] ; N[0] ; clk ;
; N/A ; None ; -7.851 ns ; key_in[6] ; F[1] ; clk ;
; N/A ; None ; -7.916 ns ; key_in[9] ; N[1] ; clk ;
; N/A ; None ; -7.967 ns ; key_in[4] ; F[2] ; clk ;
; N/A ; None ; -7.971 ns ; key_in[4] ; F[3] ; clk ;
; N/A ; None ; -7.987 ns ; key_in[2] ; N[3] ; clk ;
; N/A ; None ; -8.110 ns ; key_in[6] ; N[3] ; clk ;
; N/A ; None ; -8.212 ns ; key_in[2] ; F[1] ; clk ;
; N/A ; None ; -8.442 ns ; key_in[4] ; N[3] ; clk ;
; N/A ; None ; -8.569 ns ; key_in[3] ; F[2] ; clk ;
; N/A ; None ; -8.573 ns ; key_in[3] ; F[3] ; clk ;
; N/A ; None ; -8.623 ns ; key_in[4] ; F[0] ; clk ;
; N/A ; None ; -9.195 ns ; key_in[4] ; F[1] ; clk ;
; N/A ; None ; -9.225 ns ; key_in[3] ; F[0] ; clk ;
; N/A ; None ; -9.797 ns ; key_in[3] ; F[1] ; clk ;
+---------------+-------------+-----------+------------+------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Wed Dec 06 20:47:51 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dljpym -c dljpym --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "N[0]" and destination register "N[0]"
Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.862 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y4_N1; Fanout = 3; REG Node = 'N[0]'
Info: 2: + IC(0.553 ns) + CELL(0.309 ns) = 0.862 ns; Loc. = LC_X15_Y4_N1; Fanout = 3; REG Node = 'N[0]'
Info: Total cell delay = 0.309 ns ( 35.85 % )
Info: Total interconnect delay = 0.553 ns ( 64.15 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.743 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y4_N1; Fanout = 3; REG Node = 'N[0]'
Info: Total cell delay = 2.180 ns ( 79.48 % )
Info: Total interconnect delay = 0.563 ns ( 20.52 % )
Info: - Longest clock path from clock "clk" to source register is 2.743 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y4_N1; Fanout = 3; REG Node = 'N[0]'
Info: Total cell delay = 2.180 ns ( 79.48 % )
Info: Total interconnect delay = 0.563 ns ( 20.52 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "N[3]" (data pin = "key_in[9]", clock pin = "clk") is 13.094 ns
Info: + Longest pin to register delay is 15.800 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_51; Fanout = 4; PIN Node = 'key_in[9]'
Info: 2: + IC(5.946 ns) + CELL(0.590 ns) = 8.011 ns; Loc. = LC_X16_Y4_N1; Fanout = 3; COMB Node = 'Equal10~46'
Info: 3: + IC(0.445 ns) + CELL(0.114 ns) = 8.570 ns; Loc. = LC_X16_Y4_N7; Fanout = 4; COMB Node = 'Equal2~75'
Info: 4: + IC(1.287 ns) + CELL(0.292 ns) = 10.149 ns; Loc. = LC_X16_Y6_N8; Fanout = 2; COMB Node = 'Equal2~76'
Info: 5: + IC(1.263 ns) + CELL(0.590 ns) = 12.002 ns; Loc. = LC_X16_Y5_N6; Fanout = 4; COMB Node = 'Equal3~70'
Info: 6: + IC(0.430 ns) + CELL(0.114 ns) = 12.546 ns; Loc. = LC_X16_Y5_N8; Fanout = 2; COMB Node = 'Equal4~66'
Info: 7: + IC(1.594 ns) + CELL(0.442 ns) = 14.582 ns; Loc. = LC_X15_Y4_N9; Fanout = 4; COMB Node = 'WideNor0'
Info: 8: + IC(0.480 ns) + CELL(0.738 ns) = 15.800 ns; Loc. = LC_X15_Y4_N5; Fanout = 3; REG Node = 'N[3]'
Info: Total cell delay = 4.355 ns ( 27.56 % )
Info: Total interconnect delay = 11.445 ns ( 72.44 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "clk" to destination register is 2.743 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y4_N5; Fanout = 3; REG Node = 'N[3]'
Info: Total cell delay = 2.180 ns ( 79.48 % )
Info: Total interconnect delay = 0.563 ns ( 20.52 % )
Info: tco from clock "clk" to destination pin "flag_f" through register "F[0]" is 9.437 ns
Info: + Longest clock path from clock "clk" to source register is 2.743 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X16_Y4_N2; Fanout = 2; REG Node = 'F[0]'
Info: Total cell delay = 2.180 ns ( 79.48 % )
Info: Total interconnect delay = 0.563 ns ( 20.52 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 6.470 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y4_N2; Fanout = 2; REG Node = 'F[0]'
Info: 2: + IC(1.306 ns) + CELL(0.590 ns) = 1.896 ns; Loc. = LC_X16_Y6_N4; Fanout = 1; COMB Node = 'ff~0'
Info: 3: + IC(2.450 ns) + CELL(2.124 ns) = 6.470 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'flag_f'
Info: Total cell delay = 2.714 ns ( 41.95 % )
Info: Total interconnect delay = 3.756 ns ( 58.05 % )
Info: th for register "N[2]" (data pin = "key_in[0]", clock pin = "clk") is -3.060 ns
Info: + Longest clock path from clock "clk" to destination register is 2.743 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y4_N0; Fanout = 3; REG Node = 'N[2]'
Info: Total cell delay = 2.180 ns ( 79.48 % )
Info: Total interconnect delay = 0.563 ns ( 20.52 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 5.818 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 5; PIN Node = 'key_in[0]'
Info: 2: + IC(2.065 ns) + CELL(0.292 ns) = 3.826 ns; Loc. = LC_X16_Y5_N2; Fanout = 2; COMB Node = 'Equal5~68'
Info: 3: + IC(1.254 ns) + CELL(0.738 ns) = 5.818 ns; Loc. = LC_X15_Y4_N0; Fanout = 3; REG Node = 'N[2]'
Info: Total cell delay = 2.499 ns ( 42.95 % )
Info: Total interconnect delay = 3.319 ns ( 57.05 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Wed Dec 06 20:47:51 2006
Info: Elapsed time: 00:00:01
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