dljpym.vhd

来自「基于可编程逻辑器件FPGA的独立式键盘设计」· VHDL 代码 · 共 55 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dljpym is
	port(clk:in std_logic;
		key_in:in std_logic_vector(13 downto 0);
		data_n:out std_logic_vector(3 downto 0);
		data_f:out std_logic_vector(3 downto 0);
		flag_n:out std_logic;
		flag_f:out std_logic);
	end entity dljpym;
architecture art of dljpym is
	SIGNAL N,F:STD_LOGIC_VECTOR(3 downto 0);
	signal fn,ff:std_logic;
	signal z:std_logic_vector(13 downto 0);
begin
z<=key_in;
	process(clk)
		begin
		if clk'event and clk='1' then
			case z is
				when"00000000000001"=>n<="0000";
				when"00000000000010"=>n<="0001";
				when"00000000000100"=>n<="0010";
				when"00000000001000"=>n<="0011";
				when"00000000010000"=>n<="0100";
				when"00000000100000"=>n<="0101";
				when"00000001000000"=>n<="0110";
				when"00000010000000"=>n<="0111";
				when"00000100000000"=>n<="1000";
				when"00001000000000"=>n<="1001";
				when others=>null;--n<="1111";
			end case;
		end if;
		if clk'event and clk='1' then
			case z is
				when"00010000000000"=>f<="0001";
				when"00100000000000"=>f<="0010";
				when"01000000000000"=>f<="0100";
				when"10000000000000"=>f<="1000";
				when others=>f<="0000";
			end case;
		end if;
	
	
	end process;
	fn<=not (n(3)and n(2)and n(1)and n(0));
	ff<=f(2)or f(0);
	flag_n<=fn;
	flag_f<=ff;
	data_n<=n;
	data_f<=f;
	end architecture art;