ir.map.summary

利用Verilig编写CPLD读写EEPROM（74LC21）程序

Flow Status : Successful - Wed May 30 21:56:14 2007
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : IR
Top-level Entity Name : IR
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 0
Total pins : 10
Total virtual pins : 0
UFM blocks : 0