ir.fit.eqn
来自「利用Verilig编写CPLD读写EEPROM(74LC21)程序」· EQN 代码 · 共 74 行
EQN
74 行
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--clkfast is clkfast at PIN_21
--operation mode is input
clkfast = INPUT();
--IRInput is IRInput at PIN_38
--operation mode is input
IRInput = INPUT();
--LED[0] is LED[0] at PIN_4
--operation mode is output
LED[0] = OUTPUT(!IRInput);
--LED[1] is LED[1] at PIN_82
--operation mode is output
LED[1] = OUTPUT(GND);
--LED[2] is LED[2] at PIN_81
--operation mode is output
LED[2] = OUTPUT(GND);
--LED[3] is LED[3] at PIN_53
--operation mode is output
LED[3] = OUTPUT(GND);
--LED[4] is LED[4] at PIN_14
--operation mode is output
LED[4] = OUTPUT(GND);
--LED[5] is LED[5] at PIN_7
--operation mode is output
LED[5] = OUTPUT(GND);
--LED[6] is LED[6] at PIN_55
--operation mode is output
LED[6] = OUTPUT(GND);
--LED[7] is LED[7] at PIN_74
--operation mode is output
LED[7] = OUTPUT(GND);
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