ir.v

来自「利用Verilig编写CPLD读写EEPROM（74LC21）程序」· Verilog 代码 · 共 21 行

module IR
	(
		IRInput,
		LED,
		clkfast
	);

	input	IRInput;
	input	clkfast;
	output[7:0]	LED;

	// Wire Declaration
	assign LED[0] = !IRInput;
	// Integer Declaration

	// Concurrent Assignment

	// Always Construct

endmodule