ir.fit.rpt

利用Verilig编写CPLD读写EEPROM（74LC21）程序

; 89       ; 73         ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 90       ; 74         ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 91       ; 75         ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 92       ; 76         ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 93       ;            ;          ; GNDIO          ; gnd    ;              ;         ; --         ;                 ;
; 94       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ;
; 95       ; 77         ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 96       ; 78         ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 97       ; 79         ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 98       ; 80         ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 99       ; 81         ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 100      ; 82         ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+


+-------------------------------------------------------------+
; Output Pin Default Load For Reported TCO                    ;
+----------------------------+-------+------------------------+
; I/O Standard               ; Load  ; Termination Resistance ;
+----------------------------+-------+------------------------+
; LVTTL                      ; 10 pF ; Not Available          ;
; LVCMOS                     ; 10 pF ; Not Available          ;
; 2.5 V                      ; 10 pF ; Not Available          ;
; 1.8 V                      ; 10 pF ; Not Available          ;
; 1.5 V                      ; 10 pF ; Not Available          ;
; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available          ;
; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available          ;
+----------------------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |IR                        ; 0 (0)       ; 0            ; 0          ; 10   ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |IR                 ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------+
; Delay Chain Summary                ;
+---------+----------+---------------+
; Name    ; Pin Type ; Pad to Core 0 ;
+---------+----------+---------------+
; clkfast ; Input    ; 0             ;
; IRInput ; Input    ; 0             ;
; LED[0]  ; Output   ; --            ;
; LED[1]  ; Output   ; --            ;
; LED[2]  ; Output   ; --            ;
; LED[3]  ; Output   ; --            ;
; LED[4]  ; Output   ; --            ;
; LED[5]  ; Output   ; --            ;
; LED[6]  ; Output   ; --            ;
; LED[7]  ; Output   ; --            ;
+---------+----------+---------------+


+---------------------------------+
; Non-Global High Fan-Out Signals ;
+---------+-----------------------+
; Name    ; Fan-Out               ;
+---------+-----------------------+
; IRInput ; 1                     ;
+---------+-----------------------+


+------------------------------------------------+
; Interconnect Usage Summary                     ;
+----------------------------+-------------------+
; Interconnect Resource Type ; Usage             ;
+----------------------------+-------------------+
; C4s                        ; 1 / 784 ( < 1 % ) ;
; Direct links               ; 0 / 888 ( 0 % )   ;
; Global clocks              ; 0 / 4 ( 0 % )     ;
; LAB clocks                 ; 0 / 32 ( 0 % )    ;
; LUT chains                 ; 0 / 216 ( 0 % )   ;
; Local interconnects        ; 1 / 888 ( < 1 % ) ;
; R4s                        ; 1 / 704 ( < 1 % ) ;
+----------------------------+-------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Wed May 30 21:56:16 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off IR -c IR
Info: Selected device EPM240T100C5 for design "IR"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: No exact pin location assignment(s) for 8 pins of 10 total pins
    Info: Pin LED[1] not assigned to an exact location on the device
    Info: Pin LED[2] not assigned to an exact location on the device
    Info: Pin LED[3] not assigned to an exact location on the device
    Info: Pin LED[4] not assigned to an exact location on the device
    Info: Pin LED[5] not assigned to an exact location on the device
    Info: Pin LED[6] not assigned to an exact location on the device
    Info: Pin LED[7] not assigned to an exact location on the device
    Info: Pin clkfast not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 8 (unused VREF, 3.30 VCCIO, 1 input, 7 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 2 total pin(s) used --  36 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is pin to pin delay of 6.027 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_38; Fanout = 1; PIN Node = 'IRInput'
    Info: 2: + IC(2.573 ns) + CELL(2.322 ns) = 6.027 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'LED[0]'
    Info: Total cell delay = 3.454 ns ( 57.31 % )
    Info: Total interconnect delay = 2.573 ns ( 42.69 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Wed May 30 21:56:17 2007
    Info: Elapsed time: 00:00:02