senduard.tan.qmsg

利用VHDL实现CPLD（EPM240T100C5）的串口发送程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk50 sdo sdo~reg0 23.326 ns register " "Info: tco from clock \"clk50\" to destination pin \"sdo\" through register \"sdo~reg0\" is 23.326 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50 source 17.885 ns + Longest register " "Info: + Longest clock path from clock \"clk50\" to source register is 17.885 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50 } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.422 ns) + CELL(1.294 ns) 4.879 ns clk 2 REG LC_X2_Y4_N6 10 " "Info: 2: + IC(2.422 ns) + CELL(1.294 ns) = 4.879 ns; Loc. = LC_X2_Y4_N6; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.716 ns" { clk50 clk } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.536 ns) + CELL(1.294 ns) 9.709 ns clk16x 3 REG LC_X3_Y3_N8 9 " "Info: 3: + IC(3.536 ns) + CELL(1.294 ns) = 9.709 ns; Loc. = LC_X3_Y3_N8; Fanout = 9; REG Node = 'clk16x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.830 ns" { clk clk16x } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.223 ns) + CELL(1.294 ns) 14.226 ns clkdiv\[3\] 4 REG LC_X2_Y3_N7 15 " "Info: 4: + IC(3.223 ns) + CELL(1.294 ns) = 14.226 ns; Loc. = LC_X2_Y3_N7; Fanout = 15; REG Node = 'clkdiv\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.517 ns" { clk16x clkdiv[3] } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.741 ns) + CELL(0.918 ns) 17.885 ns sdo~reg0 5 REG LC_X6_Y2_N9 2 " "Info: 5: + IC(2.741 ns) + CELL(0.918 ns) = 17.885 ns; Loc. = LC_X6_Y2_N9; Fanout = 2; REG Node = 'sdo~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.659 ns" { clkdiv[3] sdo~reg0 } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 33.34 % ) " "Info: Total cell delay = 5.963 ns ( 33.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.922 ns ( 66.66 % ) " "Info: Total interconnect delay = 11.922 ns ( 66.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.885 ns" { clk50 clk clk16x clkdiv[3] sdo~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "17.885 ns" { clk50 clk50~combout clk clk16x clkdiv[3] sdo~reg0 } { 0.000ns 0.000ns 2.422ns 3.536ns 3.223ns 2.741ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 131 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.065 ns + Longest register pin " "Info: + Longest register to pin delay is 5.065 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sdo~reg0 1 REG LC_X6_Y2_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N9; Fanout = 2; REG Node = 'sdo~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sdo~reg0 } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.743 ns) + CELL(2.322 ns) 5.065 ns sdo 2 PIN PIN_2 0 " "Info: 2: + IC(2.743 ns) + CELL(2.322 ns) = 5.065 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'sdo'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.065 ns" { sdo~reg0 sdo } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 45.84 % ) " "Info: Total cell delay = 2.322 ns ( 45.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.743 ns ( 54.16 % ) " "Info: Total interconnect delay = 2.743 ns ( 54.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.065 ns" { sdo~reg0 sdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.065 ns" { sdo~reg0 sdo } { 0.000ns 2.743ns } { 0.000ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.885 ns" { clk50 clk clk16x clkdiv[3] sdo~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "17.885 ns" { clk50 clk50~combout clk clk16x clkdiv[3] sdo~reg0 } { 0.000ns 0.000ns 2.422ns 3.536ns 3.223ns 2.741ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.065 ns" { sdo~reg0 sdo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.065 ns" { sdo~reg0 sdo } { 0.000ns 2.743ns } { 0.000ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "wrn1 wrn clk50 9.369 ns register " "Info: th for register \"wrn1\" (data pin = \"wrn\", clock pin = \"clk50\") is 9.369 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50 destination 13.850 ns + Longest register " "Info: + Longest clock path from clock \"clk50\" to destination register is 13.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50 } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.422 ns) + CELL(1.294 ns) 4.879 ns clk 2 REG LC_X2_Y4_N6 10 " "Info: 2: + IC(2.422 ns) + CELL(1.294 ns) = 4.879 ns; Loc. = LC_X2_Y4_N6; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.716 ns" { clk50 clk } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.536 ns) + CELL(1.294 ns) 9.709 ns clk16x 3 REG LC_X3_Y3_N8 9 " "Info: 3: + IC(3.536 ns) + CELL(1.294 ns) = 9.709 ns; Loc. = LC_X3_Y3_N8; Fanout = 9; REG Node = 'clk16x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.830 ns" { clk clk16x } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.223 ns) + CELL(0.918 ns) 13.850 ns wrn1 4 REG LC_X2_Y3_N0 3 " "Info: 4: + IC(3.223 ns) + CELL(0.918 ns) = 13.850 ns; Loc. = LC_X2_Y3_N0; Fanout = 3; REG Node = 'wrn1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.141 ns" { clk16x wrn1 } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 33.71 % ) " "Info: Total cell delay = 4.669 ns ( 33.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.181 ns ( 66.29 % ) " "Info: Total interconnect delay = 9.181 ns ( 66.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.850 ns" { clk50 clk clk16x wrn1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "13.850 ns" { clk50 clk50~combout clk clk16x wrn1 } { 0.000ns 0.000ns 2.422ns 3.536ns 3.223ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 46 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.702 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.702 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns wrn 1 CLK PIN_81 9 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_81; Fanout = 9; CLK Node = 'wrn'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { wrn } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.766 ns) + CELL(0.804 ns) 4.702 ns wrn1 2 REG LC_X2_Y3_N0 3 " "Info: 2: + IC(2.766 ns) + CELL(0.804 ns) = 4.702 ns; Loc. = LC_X2_Y3_N0; Fanout = 3; REG Node = 'wrn1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.570 ns" { wrn wrn1 } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.936 ns ( 41.17 % ) " "Info: Total cell delay = 1.936 ns ( 41.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.766 ns ( 58.83 % ) " "Info: Total interconnect delay = 2.766 ns ( 58.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.702 ns" { wrn wrn1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.702 ns" { wrn wrn~combout wrn1 } { 0.000ns 0.000ns 2.766ns } { 0.000ns 1.132ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.850 ns" { clk50 clk clk16x wrn1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "13.850 ns" { clk50 clk50~combout clk clk16x wrn1 } { 0.000ns 0.000ns 2.422ns 3.536ns 3.223ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.702 ns" { wrn wrn1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.702 ns" { wrn wrn~combout wrn1 } { 0.000ns 0.000ns 2.766ns } { 0.000ns 1.132ns 0.804ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 25 18:55:05 2007 " "Info: Processing ended: Sun Nov 25 18:55:05 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}