senduard.tan.qmsg

利用VHDL实现CPLD（EPM240T100C5）的串口发送程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk50 " "Info: Assuming node \"clk50\" is an undefined clock" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 31 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk50" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wrn " "Info: Assuming node \"wrn\" is an undefined clock" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 32 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "wrn" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk " "Info: Detected ripple clock \"clk\" as buffer" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 50 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkdiv\[3\] " "Info: Detected ripple clock \"clkdiv\[3\]\" as buffer" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 42 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkdiv\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk16x " "Info: Detected ripple clock \"clk16x\" as buffer" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 48 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk16x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk50 register no_bits_sent\[0\] register sdo~reg0 81.82 MHz 12.222 ns Internal " "Info: Clock \"clk50\" has Internal fmax of 81.82 MHz between source register \"no_bits_sent\[0\]\" and destination register \"sdo~reg0\" (period= 12.222 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.402 ns + Longest register register " "Info: + Longest register to register delay is 5.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns no_bits_sent\[0\] 1 REG LC_X6_Y2_N5 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N5; Fanout = 11; REG Node = 'no_bits_sent\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { no_bits_sent[0] } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 175 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.894 ns) + CELL(0.740 ns) 2.634 ns always6~55 2 COMB LC_X6_Y2_N6 2 " "Info: 2: + IC(1.894 ns) + CELL(0.740 ns) = 2.634 ns; Loc. = LC_X6_Y2_N6; Fanout = 2; COMB Node = 'always6~55'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.634 ns" { no_bits_sent[0] always6~55 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.132 ns) + CELL(0.740 ns) 4.506 ns sdo~312 3 COMB LC_X6_Y2_N8 1 " "Info: 3: + IC(1.132 ns) + CELL(0.740 ns) = 4.506 ns; Loc. = LC_X6_Y2_N8; Fanout = 1; COMB Node = 'sdo~312'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.872 ns" { always6~55 sdo~312 } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 5.402 ns sdo~reg0 4 REG LC_X6_Y2_N9 2 " "Info: 4: + IC(0.305 ns) + CELL(0.591 ns) = 5.402 ns; Loc. = LC_X6_Y2_N9; Fanout = 2; REG Node = 'sdo~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.896 ns" { sdo~312 sdo~reg0 } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.071 ns ( 38.34 % ) " "Info: Total cell delay = 2.071 ns ( 38.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.331 ns ( 61.66 % ) " "Info: Total interconnect delay = 3.331 ns ( 61.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.402 ns" { no_bits_sent[0] always6~55 sdo~312 sdo~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.402 ns" { no_bits_sent[0] always6~55 sdo~312 sdo~reg0 } { 0.000ns 1.894ns 1.132ns 0.305ns } { 0.000ns 0.740ns 0.740ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50 destination 17.885 ns + Shortest register " "Info: + Shortest clock path from clock \"clk50\" to destination register is 17.885 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50 } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.422 ns) + CELL(1.294 ns) 4.879 ns clk 2 REG LC_X2_Y4_N6 10 " "Info: 2: + IC(2.422 ns) + CELL(1.294 ns) = 4.879 ns; Loc. = LC_X2_Y4_N6; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.716 ns" { clk50 clk } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.536 ns) + CELL(1.294 ns) 9.709 ns clk16x 3 REG LC_X3_Y3_N8 9 " "Info: 3: + IC(3.536 ns) + CELL(1.294 ns) = 9.709 ns; Loc. = LC_X3_Y3_N8; Fanout = 9; REG Node = 'clk16x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.830 ns" { clk clk16x } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.223 ns) + CELL(1.294 ns) 14.226 ns clkdiv\[3\] 4 REG LC_X2_Y3_N7 15 " "Info: 4: + IC(3.223 ns) + CELL(1.294 ns) = 14.226 ns; Loc. = LC_X2_Y3_N7; Fanout = 15; REG Node = 'clkdiv\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.517 ns" { clk16x clkdiv[3] } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.741 ns) + CELL(0.918 ns) 17.885 ns sdo~reg0 5 REG LC_X6_Y2_N9 2 " "Info: 5: + IC(2.741 ns) + CELL(0.918 ns) = 17.885 ns; Loc. = LC_X6_Y2_N9; Fanout = 2; REG Node = 'sdo~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.659 ns" { clkdiv[3] sdo~reg0 } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 33.34 % ) " "Info: Total cell delay = 5.963 ns ( 33.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.922 ns ( 66.66 % ) " "Info: Total interconnect delay = 11.922 ns ( 66.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.885 ns" { clk50 clk clk16x clkdiv[3] sdo~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "17.885 ns" { clk50 clk50~combout clk clk16x clkdiv[3] sdo~reg0 } { 0.000ns 0.000ns 2.422ns 3.536ns 3.223ns 2.741ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50 source 17.885 ns - Longest register " "Info: - Longest clock path from clock \"clk50\" to source register is 17.885 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50 } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.422 ns) + CELL(1.294 ns) 4.879 ns clk 2 REG LC_X2_Y4_N6 10 " "Info: 2: + IC(2.422 ns) + CELL(1.294 ns) = 4.879 ns; Loc. = LC_X2_Y4_N6; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.716 ns" { clk50 clk } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.536 ns) + CELL(1.294 ns) 9.709 ns clk16x 3 REG LC_X3_Y3_N8 9 " "Info: 3: + IC(3.536 ns) + CELL(1.294 ns) = 9.709 ns; Loc. = LC_X3_Y3_N8; Fanout = 9; REG Node = 'clk16x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.830 ns" { clk clk16x } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.223 ns) + CELL(1.294 ns) 14.226 ns clkdiv\[3\] 4 REG LC_X2_Y3_N7 15 " "Info: 4: + IC(3.223 ns) + CELL(1.294 ns) = 14.226 ns; Loc. = LC_X2_Y3_N7; Fanout = 15; REG Node = 'clkdiv\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.517 ns" { clk16x clkdiv[3] } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.741 ns) + CELL(0.918 ns) 17.885 ns no_bits_sent\[0\] 5 REG LC_X6_Y2_N5 11 " "Info: 5: + IC(2.741 ns) + CELL(0.918 ns) = 17.885 ns; Loc. = LC_X6_Y2_N5; Fanout = 11; REG Node = 'no_bits_sent\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.659 ns" { clkdiv[3] no_bits_sent[0] } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 175 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 33.34 % ) " "Info: Total cell delay = 5.963 ns ( 33.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.922 ns ( 66.66 % ) " "Info: Total interconnect delay = 11.922 ns ( 66.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.885 ns" { clk50 clk clk16x clkdiv[3] no_bits_sent[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "17.885 ns" { clk50 clk50~combout clk clk16x clkdiv[3] no_bits_sent[0] } { 0.000ns 0.000ns 2.422ns 3.536ns 3.223ns 2.741ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.885 ns" { clk50 clk clk16x clkdiv[3] sdo~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "17.885 ns" { clk50 clk50~combout clk clk16x clkdiv[3] sdo~reg0 } { 0.000ns 0.000ns 2.422ns 3.536ns 3.223ns 2.741ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.885 ns" { clk50 clk clk16x clkdiv[3] no_bits_sent[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "17.885 ns" { clk50 clk50~combout clk clk16x clkdiv[3] no_bits_sent[0] } { 0.000ns 0.000ns 2.422ns 3.536ns 3.223ns 2.741ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 175 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 131 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 175 -1 0 } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 131 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.402 ns" { no_bits_sent[0] always6~55 sdo~312 sdo~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.402 ns" { no_bits_sent[0] always6~55 sdo~312 sdo~reg0 } { 0.000ns 1.894ns 1.132ns 0.305ns } { 0.000ns 0.740ns 0.740ns 0.591ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.885 ns" { clk50 clk clk16x clkdiv[3] sdo~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "17.885 ns" { clk50 clk50~combout clk clk16x clkdiv[3] sdo~reg0 } { 0.000ns 0.000ns 2.422ns 3.536ns 3.223ns 2.741ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.885 ns" { clk50 clk clk16x clkdiv[3] no_bits_sent[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "17.885 ns" { clk50 clk50~combout clk clk16x clkdiv[3] no_bits_sent[0] } { 0.000ns 0.000ns 2.422ns 3.536ns 3.223ns 2.741ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "wrn " "Info: No valid register-to-register data paths exist for clock \"wrn\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "tbr\[1\] din\[1\] wrn 0.512 ns register " "Info: tsu for register \"tbr\[1\]\" (data pin = \"din\[1\]\", clock pin = \"wrn\") is 0.512 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.387 ns + Longest pin register " "Info: + Longest pin to register delay is 6.387 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns din\[1\] 1 PIN PIN_29 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'din\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { din[1] } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.975 ns) + CELL(0.280 ns) 6.387 ns tbr\[1\] 2 REG LC_X5_Y2_N4 2 " "Info: 2: + IC(4.975 ns) + CELL(0.280 ns) = 6.387 ns; Loc. = LC_X5_Y2_N4; Fanout = 2; REG Node = 'tbr\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.255 ns" { din[1] tbr[1] } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 22.11 % ) " "Info: Total cell delay = 1.412 ns ( 22.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.975 ns ( 77.89 % ) " "Info: Total interconnect delay = 4.975 ns ( 77.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.387 ns" { din[1] tbr[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.387 ns" { din[1] din[1]~combout tbr[1] } { 0.000ns 0.000ns 4.975ns } { 0.000ns 1.132ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 114 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrn destination 6.208 ns - Shortest register " "Info: - Shortest clock path from clock \"wrn\" to destination register is 6.208 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns wrn 1 CLK PIN_81 9 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_81; Fanout = 9; CLK Node = 'wrn'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { wrn } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.158 ns) + CELL(0.918 ns) 6.208 ns tbr\[1\] 2 REG LC_X5_Y2_N4 2 " "Info: 2: + IC(4.158 ns) + CELL(0.918 ns) = 6.208 ns; Loc. = LC_X5_Y2_N4; Fanout = 2; REG Node = 'tbr\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.076 ns" { wrn tbr[1] } "NODE_NAME" } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 33.02 % ) " "Info: Total cell delay = 2.050 ns ( 33.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.158 ns ( 66.98 % ) " "Info: Total interconnect delay = 4.158 ns ( 66.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.208 ns" { wrn tbr[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.208 ns" { wrn wrn~combout tbr[1] } { 0.000ns 0.000ns 4.158ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.387 ns" { din[1] tbr[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.387 ns" { din[1] din[1]~combout tbr[1] } { 0.000ns 0.000ns 4.975ns } { 0.000ns 1.132ns 0.280ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.208 ns" { wrn tbr[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.208 ns" { wrn wrn~combout tbr[1] } { 0.000ns 0.000ns 4.158ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}