senduard.tan.rpt

利用VHDL实现CPLD（EPM240T100C5）的串口发送程序

; N/A           ; None        ; 0.042 ns  ; din[1] ; tbr[1] ; wrn      ;
+---------------+-------------+-----------+--------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Nov 25 18:55:04 2007
Info: Command: quartus_tan --lower_priority --read_settings_files=off --write_settings_files=off senduard -c senduard
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk50" is an undefined clock
    Info: Assuming node "wrn" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk" as buffer
    Info: Detected ripple clock "clkdiv[3]" as buffer
    Info: Detected ripple clock "clk16x" as buffer
Info: Clock "clk50" has Internal fmax of 81.82 MHz between source register "no_bits_sent[0]" and destination register "sdo~reg0" (period= 12.222 ns)
    Info: + Longest register to register delay is 5.402 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N5; Fanout = 11; REG Node = 'no_bits_sent[0]'
        Info: 2: + IC(1.894 ns) + CELL(0.740 ns) = 2.634 ns; Loc. = LC_X6_Y2_N6; Fanout = 2; COMB Node = 'always6~55'
        Info: 3: + IC(1.132 ns) + CELL(0.740 ns) = 4.506 ns; Loc. = LC_X6_Y2_N8; Fanout = 1; COMB Node = 'sdo~312'
        Info: 4: + IC(0.305 ns) + CELL(0.591 ns) = 5.402 ns; Loc. = LC_X6_Y2_N9; Fanout = 2; REG Node = 'sdo~reg0'
        Info: Total cell delay = 2.071 ns ( 38.34 % )
        Info: Total interconnect delay = 3.331 ns ( 61.66 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk50" to destination register is 17.885 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'
            Info: 2: + IC(2.422 ns) + CELL(1.294 ns) = 4.879 ns; Loc. = LC_X2_Y4_N6; Fanout = 10; REG Node = 'clk'
            Info: 3: + IC(3.536 ns) + CELL(1.294 ns) = 9.709 ns; Loc. = LC_X3_Y3_N8; Fanout = 9; REG Node = 'clk16x'
            Info: 4: + IC(3.223 ns) + CELL(1.294 ns) = 14.226 ns; Loc. = LC_X2_Y3_N7; Fanout = 15; REG Node = 'clkdiv[3]'
            Info: 5: + IC(2.741 ns) + CELL(0.918 ns) = 17.885 ns; Loc. = LC_X6_Y2_N9; Fanout = 2; REG Node = 'sdo~reg0'
            Info: Total cell delay = 5.963 ns ( 33.34 % )
            Info: Total interconnect delay = 11.922 ns ( 66.66 % )
        Info: - Longest clock path from clock "clk50" to source register is 17.885 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'
            Info: 2: + IC(2.422 ns) + CELL(1.294 ns) = 4.879 ns; Loc. = LC_X2_Y4_N6; Fanout = 10; REG Node = 'clk'
            Info: 3: + IC(3.536 ns) + CELL(1.294 ns) = 9.709 ns; Loc. = LC_X3_Y3_N8; Fanout = 9; REG Node = 'clk16x'
            Info: 4: + IC(3.223 ns) + CELL(1.294 ns) = 14.226 ns; Loc. = LC_X2_Y3_N7; Fanout = 15; REG Node = 'clkdiv[3]'
            Info: 5: + IC(2.741 ns) + CELL(0.918 ns) = 17.885 ns; Loc. = LC_X6_Y2_N5; Fanout = 11; REG Node = 'no_bits_sent[0]'
            Info: Total cell delay = 5.963 ns ( 33.34 % )
            Info: Total interconnect delay = 11.922 ns ( 66.66 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: No valid register-to-register data paths exist for clock "wrn"
Info: tsu for register "tbr[1]" (data pin = "din[1]", clock pin = "wrn") is 0.512 ns
    Info: + Longest pin to register delay is 6.387 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'din[1]'
        Info: 2: + IC(4.975 ns) + CELL(0.280 ns) = 6.387 ns; Loc. = LC_X5_Y2_N4; Fanout = 2; REG Node = 'tbr[1]'
        Info: Total cell delay = 1.412 ns ( 22.11 % )
        Info: Total interconnect delay = 4.975 ns ( 77.89 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "wrn" to destination register is 6.208 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_81; Fanout = 9; CLK Node = 'wrn'
        Info: 2: + IC(4.158 ns) + CELL(0.918 ns) = 6.208 ns; Loc. = LC_X5_Y2_N4; Fanout = 2; REG Node = 'tbr[1]'
        Info: Total cell delay = 2.050 ns ( 33.02 % )
        Info: Total interconnect delay = 4.158 ns ( 66.98 % )
Info: tco from clock "clk50" to destination pin "sdo" through register "sdo~reg0" is 23.326 ns
    Info: + Longest clock path from clock "clk50" to source register is 17.885 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'
        Info: 2: + IC(2.422 ns) + CELL(1.294 ns) = 4.879 ns; Loc. = LC_X2_Y4_N6; Fanout = 10; REG Node = 'clk'
        Info: 3: + IC(3.536 ns) + CELL(1.294 ns) = 9.709 ns; Loc. = LC_X3_Y3_N8; Fanout = 9; REG Node = 'clk16x'
        Info: 4: + IC(3.223 ns) + CELL(1.294 ns) = 14.226 ns; Loc. = LC_X2_Y3_N7; Fanout = 15; REG Node = 'clkdiv[3]'
        Info: 5: + IC(2.741 ns) + CELL(0.918 ns) = 17.885 ns; Loc. = LC_X6_Y2_N9; Fanout = 2; REG Node = 'sdo~reg0'
        Info: Total cell delay = 5.963 ns ( 33.34 % )
        Info: Total interconnect delay = 11.922 ns ( 66.66 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 5.065 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N9; Fanout = 2; REG Node = 'sdo~reg0'
        Info: 2: + IC(2.743 ns) + CELL(2.322 ns) = 5.065 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'sdo'
        Info: Total cell delay = 2.322 ns ( 45.84 % )
        Info: Total interconnect delay = 2.743 ns ( 54.16 % )
Info: th for register "wrn1" (data pin = "wrn", clock pin = "clk50") is 9.369 ns
    Info: + Longest clock path from clock "clk50" to destination register is 13.850 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'
        Info: 2: + IC(2.422 ns) + CELL(1.294 ns) = 4.879 ns; Loc. = LC_X2_Y4_N6; Fanout = 10; REG Node = 'clk'
        Info: 3: + IC(3.536 ns) + CELL(1.294 ns) = 9.709 ns; Loc. = LC_X3_Y3_N8; Fanout = 9; REG Node = 'clk16x'
        Info: 4: + IC(3.223 ns) + CELL(0.918 ns) = 13.850 ns; Loc. = LC_X2_Y3_N0; Fanout = 3; REG Node = 'wrn1'
        Info: Total cell delay = 4.669 ns ( 33.71 % )
        Info: Total interconnect delay = 9.181 ns ( 66.29 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 4.702 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_81; Fanout = 9; CLK Node = 'wrn'
        Info: 2: + IC(2.766 ns) + CELL(0.804 ns) = 4.702 ns; Loc. = LC_X2_Y3_N0; Fanout = 3; REG Node = 'wrn1'
        Info: Total cell delay = 1.936 ns ( 41.17 % )
        Info: Total interconnect delay = 2.766 ns ( 58.83 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sun Nov 25 18:55:05 2007
    Info: Elapsed time: 00:00:03